A Novel Zero-Aware Four-Transistor SRAM Cell for High Density and Low Power Cache Application

Based on the observation that dynamic occurrence of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS four-transistor SRAM cell (4T SRAM cell) for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. Novel 4T SRAM cell uses two word-lines and one pair bit-line. The new cell size is 20% smaller than a conventional six-transistor cell (6T SRAM cell) using same design rules and average delay access of a cache based on new 4T SRAM cell is 30% smaller than a cache based on 6T SRAM cell. Also the average dynamic energy consumption during cache access of new cell is 45% smaller than 6T SRAM cell.