Leakage immune modified pass transistor based 8t SRAM cell in subthreshold region
Article No.: 6, Page 6
Abstract
The paper presents a novel 8T SRAM cell with access pass gates replaced with modified PMOS pass transistor logic. In comparison to 6T SRAM cell, the proposed cell achieves 3.5x higher read SNM and 2.4x higher write SNM with 16.6% improved SINM (static current noise margin) distribution at the expense of 7x lower WTI (write trip current) at 0.4V power supply voltage, while maintaining similar stability in hold mode. The proposed 8T SRAM cell shows improvements in terms of 7.735x narrower spread in average standby power, 2.61x less in average TWA (write access time), and 1.07x less in average TRA (read access time) at supply voltage varying from 0.3V to 0.5V as compared to 6T SRAM equivalent at 45 nm technology node. Thus, comparative analysis shows that the proposed design has a significant improvement, thereby achieving high cell stability at 45nm technology node.
References
[1]
Y. Nakagome, M. Horiguchi, T. Kawahara, and K. Itoh, "Review and future prospects of low-voltage RAMcircuits," IBM Journal of Research and Development, vol. 47, no. 5-6, pp. 525-552, 2003.
[2]
M. Radfar, K. Shah, and J. Singh, "Recent subthreshold design techniques,"Active and Passive Electronic Components, vol. 2012, Article ID 926753, 11 pages, 2012.
[3]
S. Mukhopadhyay, S. Ghosh, K. Kim, and K. Roy, "Low-power and process variation tolerantmemories in sub-90nm technologies," in Proceedings of the IEEE International Conference on SOC, pp. 155-159, Taipei, Taiwan, September 2006.
[4]
A. J. Bhavnagarwala, X. Tang, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE Journal of Solid-State Circuits, vol. 36, no. 4, pp. 658-665, 2001.
[5]
B. H. Calhoun and A. Chandrakasan, "Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS," in Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC '05), pp. 363-366, September 2005.
[6]
H. Mizuno and T. Nagano, "Driving source-line cell architecture for sub-1-V high-speed low-power applications," IEEE Journal of Solid-State Circuits, vol. 31, no. 4, pp. 552-557, 1996.
[7]
J. Singh, D. K. Pradhan, S. Hollis, and S. P. Mohanty, "A single ended 6T SRAM cell design for ultra-low-voltage applications," IEICE Electronics Express, vol. 5, no. 18, pp. 750-755, 2008.
[8]
I. J. Chang, J.-J. Kim, S. P. Park, and K. Roy, "A 32 kb 10T subthreshold sram array with bit-interleaving and differential read scheme in 90nm CMOS," IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 650-658, 2009.
[9]
J. P. Kulkarni, K. Kim, and K. Roy, "A 160mV, fully differential, robust schmitt trigger based sub-threshold SRAM," in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '07), pp. 171-176, August 2007.
[10]
M. Zamani, S. Hassanzadeh, K. Hajsadeghi, and R. Saeidi, "A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM," in Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS '13), pp. 104-107, Abu Dhabi, United Arab Emirates, March 2013.
[11]
A. A. Mazreah, M. R. Sahebi, M. T. Manzuri, and S. J. Hosseini, "A novel zero-aware four-transistor SRAM cell for high density and low power cache application," in Proceedings of the International Conference on Advanced Computer Theory and Engineering (ICACTE '08), pp. 571-575, Phuket, Thailand, December 2008.
[12]
A. Teman, A. Mordakhay, J. Mezhibovsky, and A. Fish, "A 40 nm sub-threshold 5T SRAM bit cell with improved read and write stability," IEEE Transactions on Circuits and Systems, vol. 59, no. 12, pp. 873-877, 2012.
[13]
S. Nalam and B. H. Calhoun, "Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T," in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC'09), pp. 709-712, San Jose, Calif, USA, September 2009.
[14]
B. Zhai, D. Blaauw, D. Sylvester, and S. Hanson, "A sub-200mV 6T SRAM in 0.13µm CMOS," in Proceedings of the 54th IEEE International Solid-State Circuits Conference (ISSCC'07), pp. 332-606, IEEE, San Francisco, Calif, USA, February 2007.
[15]
K. Khare, N. Khare, V. K. Kulhade, and P. Deshpande, "VLSI design and analysis of low power 6T SRAM cell using cadence tool," in Proceedings of the IEEE International Conference on Semiconductor Electronics (ICSE'08), pp. 117-121, Johor Bahru, Malaysia, November 2008.
[16]
R. E. Aly, M. I. Faisal, and M. A. Bayoumi, "Novel 7T SRAM cell for low power cache design," in Proceedings of the IEEE International SOC Conference, pp. 171-174, Herndon, VA, USA, September 2005.
[17]
A. Islam and M. Hasan, "A technique to mitigate impact of process, voltage and temperature variations on designmetrics of SRAM Cell," Microelectronics Reliability, vol. 52, no. 2, pp. 405- 411, 2012.
[18]
J. P. Kulkarni, K. Kim, and K. Roy, "A 160 mV robust schmitt trigger based subthreshold SRAM," IEEE Journal of Solid-State Circuits, vol. 42, no. 10, pp. 2303-2313, 2007.
[19]
E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE Journal of Solid-State Circuits, vol. 22, no. 5, pp. 748-754, 1987.
[20]
B. H. Calhoun and A. P. Chandrakasan, "Static noise margin variation for sub-threshold SRAM in 65-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 41, no. 7, pp. 1673-1679, 2006.
[21]
K. Zhang, U. Bhattacharya, Z. Chen et al., "A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply," IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 146-151, 2006.
[22]
E. Grossar, M. Stucchi, K. Maex, and W. Dehaene, "Read stability and write-ability analysis of SRAM cells for nanometer technologies," IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2577-2588, 2006.
[23]
S. Lin, Y.-B. Kim, and F. Lombardi, "Design and analysis of a 32nm PVT tolerant CMOS SRAM cell for low leakage and high stability," Integration, the VLSI Journal, vol. 43, no. 2, pp. 176-187, 2010.
- Leakage immune modified pass transistor based 8t SRAM cell in subthreshold region
Recommendations
Design and analysis of ultra-thin-body SOI based subthreshold SRAM
ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and designThis paper analyzes the stability, margin, and performance of Ultra-Thin-Body (UTB) SOI 6T/8T SRAM cells operating in subthreshold region. An analytical SNM model for UTB SOI 6T/8T SRAM cells operating in the subthreshold region is presented to ...
Improving the subthreshold performance of junctionless transistor using spacer engineering
In this brief, an attempt has been made to improve the ultra-low power (ULP) performance of junctionless transistor (JLT) using spacer engineering. The length of gate sidewall dual-k (high-k and low-k) spacers are optimized to improve the ULP ...
Low-leakage robust SRAM cell design for sub-100nm technologies
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation ConferenceA novel low-leakage robust SRAM design for sub-100nm technologies, Hybrid SRAM (HSRAM) cell, is presented in this paper. Leakage power, especially subthreshold leakage and gate leakage, and soft error are challenging the design of SRAM. While these ...
Comments
Information & Contributors
Information
Published In
Publisher
Hindawi Limited
London, United Kingdom
Publication History
Published: 01 January 2016
Accepted: 16 August 2015
Received: 02 June 2015
Qualifiers
- Article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 73Total Downloads
- Downloads (Last 12 months)55
- Downloads (Last 6 weeks)22
Reflects downloads up to 17 Feb 2025
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in