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Core-level modeling and frequency prediction for DSP applications on FPGAs

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Alan GeorgeAuthors Info & Claims

International Journal of Reconfigurable Computing, Volume 2015

Article No.: 7, Page 7

https://doi.org/10.1155/2015/784672

Published: 01 January 2016 Publication History

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Abstract

Field-programmable gate arrays (FPGAs) provide a promising technology that can improve performance of many high-performance computing and embedded applications. However, unlike software design tools, the relatively immature state of FPGA tools significantly limits productivity and consequently prevents widespread adoption of the technology. For example, the lengthy design-translate-execute (DTE) process often must be iterated to meet the application requirements. Previous works have enabled model-based, design-space exploration to reduce DTE iterations but are limited by a lack of accurate model-based prediction of key design parameters, the most important of which is clock frequency. In this paper, we present a core-level modeling and design (CMD) methodology that enables modeling of FPGA applications at an abstract level and yet produces accurate predictions of parameters such as clock frequency, resource utilization (i.e., area), and latency. We evaluate CMD's prediction methods using several high-performance DSP applications on various families of FPGAs and show an average clock-frequency prediction error of 3.6%, with a worst-case error of 20.4%, compared to the best of existing high-level prediction methods, 13.9% average error with 48.2% worst-case error. We also demonstrate how such prediction enables accurate design-space exploration without coding in a hardware-description language (HDL), significantly reducing the total design time.

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Cited By

Devasia JChandran PSoman AMathew AJharwal JHung CPapadopoulos G(2019)Graph sparsification with parallelization to optimize the identification of causal genes and dysregulated pathwaysProceedings of the 34th ACM/SIGAPP Symposium on Applied Computing10.1145/3297280.3297352(747-753)Online publication date: 8-Apr-2019
https://dl.acm.org/doi/10.1145/3297280.3297352

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Published In

cover image International Journal of Reconfigurable Computing

International Journal of Reconfigurable Computing Volume 2015, Issue

January 2015

188 pages

ISSN:1687-7195

EISSN:1687-7209

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Hindawi Limited

London, United Kingdom

Publication History

Published: 01 January 2016

Accepted: 10 August 2015

Received: 03 March 2015

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Cited By

Devasia JChandran PSoman AMathew AJharwal JHung CPapadopoulos G(2019)Graph sparsification with parallelization to optimize the identification of causal genes and dysregulated pathwaysProceedings of the 34th ACM/SIGAPP Symposium on Applied Computing10.1145/3297280.3297352(747-753)Online publication date: 8-Apr-2019
https://dl.acm.org/doi/10.1145/3297280.3297352

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