research-article

A framework for core-level modeling and design of reconfigurable computing algorithms

Authors:

Alan D. GeorgeAuthors Info & Claims

HPRCTA '09: Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications

Pages 29 - 38

https://doi.org/10.1145/1646461.1646465

Published: 15 November 2009 Publication History

Abstract

Reconfigurable computing (RC) is rapidly becoming a vital technology for many applications, from high-performance computing to embedded systems. The inherent advantages of custom-logic hardware devices, such as the FPGA, combined with the versatility of software-driven hardware configuration often boost performance while reducing power consumption. However, compared to software design tools, the relatively immature state of RC design tools significantly limits productivity and consequently limits widespread adoption of RC. Long and tedious design-translate-execute (DTE) processes for RC applications (e.g., using RTL through HDL) must be repeated in order to meet mission requirements. Novel methods for rapid virtual prototyping and performance prediction can reduce DTE repetitions by providing fast and accurate tradeoff analysis before the design stage. This paper presents a novel core-level modeling and design (CMD) framework for RC algorithms to support fast, accurate and early design-space exploration (DSE). The framework provides support for core-level modeling, performance prediction, and rapid bridging to design and translation. Core-level modeling enables detailed DSE without the need for coding. Performance prediction, such as maximum clock frequency, supports core-level DSE and can help system-level modeling and design tools to achieve more accurate system-level DSE. Finally, core-level models can be used to generate code templates and design constraints that feed translation tools and to rapidly obtain predicted performance.

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Cited By

Cai XHu WMa TMa R(2018)A hybrid scheduling algorithm for reconfigurable processor architecture2018 13th IEEE Conference on Industrial Electronics and Applications (ICIEA)10.1109/ICIEA.2018.8397812(745-749)Online publication date: May-2018
https://doi.org/10.1109/ICIEA.2018.8397812
Wang GStitt GLam HGeorge A(2016)Core-level modeling and frequency prediction for DSP applications on FPGAsInternational Journal of Reconfigurable Computing10.1155/2015/7846722015(7-7)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1155/2015/784672
Reardon CHolland BGeorge AStitt GLam H(2012)RCMLACM Transactions on Embedded Computing Systems10.1145/2331147.233115311:S2(1-22)Online publication date: 1-Aug-2012
https://dl.acm.org/doi/10.1145/2331147.2331153
Show More Cited By

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A framework for core-level modeling and design of reconfigurable computing algorithms

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Published In

cover image ACM Conferences

HPRCTA '09: Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications

November 2009

61 pages

ISBN:9781605587219

DOI:10.1145/1646461

General Chairs:
Volodymyr Kindratenko
NCSA, University of Illinois
,
Tarek El-Ghazawi
The George Washington University

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 15 November 2009

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Division of Engineering Education and Centers

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SC '09

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SIGARCH

SC '09: International Conference for High Performance Computing, Networking, Storage and Analysis

November 15, 2009

Oregon, Portland

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Cited By

Cai XHu WMa TMa R(2018)A hybrid scheduling algorithm for reconfigurable processor architecture2018 13th IEEE Conference on Industrial Electronics and Applications (ICIEA)10.1109/ICIEA.2018.8397812(745-749)Online publication date: May-2018
https://doi.org/10.1109/ICIEA.2018.8397812
Wang GStitt GLam HGeorge A(2016)Core-level modeling and frequency prediction for DSP applications on FPGAsInternational Journal of Reconfigurable Computing10.1155/2015/7846722015(7-7)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1155/2015/784672
Reardon CHolland BGeorge AStitt GLam H(2012)RCMLACM Transactions on Embedded Computing Systems10.1145/2331147.233115311:S2(1-22)Online publication date: 1-Aug-2012
https://dl.acm.org/doi/10.1145/2331147.2331153
Stitt GGeorge ALam HSmith MAggarwal VWang GReardon CHolland BKoehler SCoole J(2011)An End-to-End Tool Flow for FPGA-Accelerated Scientific ComputingIEEE Design & Test10.1109/MDT.2011.4628:4(68-77)Online publication date: 1-Jul-2011
https://dl.acm.org/doi/10.1109/MDT.2011.46
Hu WWang CMa JChen TChen D(2010)A Novel Approach for Finding Candidate Locations for Online FPGA PlacementProceedings of the 2010 10th IEEE International Conference on Computer and Information Technology10.1109/CIT.2010.428(2509-2515)Online publication date: 29-Jun-2010
https://dl.acm.org/doi/10.1109/CIT.2010.428

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