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10.1109/ICVD.2005.80guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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DFM: Linking Design and Manufacturing

Published: 03 January 2005 Publication History

Abstract

Until the move to the 130nm node, yield was an issue only for product engineers and engineers on the production line. Design engineers did not need to think explicitly about yield, or understand the manufacturing process. Beginning at the 130nm node, yield has become more problematic, and the defect mechanisms that contribute to yield loss are very different. Where random defects used to be dominant, we now have defects due to lithographic issues, and pattern (or design) dependent issues. This tutorial will explain how these latter defect mechanisms differ from random defects and how and why the design engineer needs to become involved to mitigate the problem. On the lithography topic, this tutorial will briefly examine techniques such as OPC (Optical Proximity Correction) and PSM (Phase Shift Masking), and explain their design and yield impact. We will also examine issues such as dummy metal fill for CMP, redundant via insertion, as ways to mitigate pattern dependent yield issues.

Cited By

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  • (2011)Simultaneous redundant via insertion and line end extension for yield optimizationProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950940(633-638)Online publication date: 25-Jan-2011
  • (2008)Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flowProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366195(359-362)Online publication date: 4-May-2008
  • (2008)Optimal post-routing redundant via insertionProceedings of the 2008 international symposium on Physical design10.1145/1353629.1353656(111-117)Online publication date: 13-Apr-2008
  • Show More Cited By

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cover image Guide Proceedings
VLSID '05: Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
January 2005
795 pages
ISBN:0769522645

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IEEE Computer Society

United States

Publication History

Published: 03 January 2005

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Cited By

View all
  • (2011)Simultaneous redundant via insertion and line end extension for yield optimizationProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950940(633-638)Online publication date: 25-Jan-2011
  • (2008)Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flowProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366195(359-362)Online publication date: 4-May-2008
  • (2008)Optimal post-routing redundant via insertionProceedings of the 2008 international symposium on Physical design10.1145/1353629.1353656(111-117)Online publication date: 13-Apr-2008
  • (2007)Conjugate conflict continuation graphs for multi-layer constrained via minimizationInformation Sciences: an International Journal10.1016/j.ins.2007.01.013177:12(2436-2447)Online publication date: 20-Jun-2007
  • (2006)Post-routing redundant via insertion and line end extension with via density considerationProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233631(633-640)Online publication date: 5-Nov-2006

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