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Post-routing redundant via insertion and line end extension with via density consideration

Published: 05 November 2006 Publication History

Abstract

Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. However, if the amount of inserted redundant vias is not well controlled, it could violate via density rules and adversely worsen the yield and reliability of the design. In this paper, we first study the problem of redundant via insertion, and present two methods to accelerate a state-of-the-art approach (which is based on a maximum independent set (MIS) formulation) to solve it. We then consider the problem of simultaneous redundant via insertion and line end extension. We formulate the problem as a maximum weighted independent set (MWIS) problem and modify the accelerated MIS-based approach to solve it. Lastly, we investigate the problem of simultaneous redundant via insertion and line end extension subject to the maximum via density rule, and present a two-stage approach for it. In the first stage, we ignore the maximum via density rule, and enhance the MWIS-based approach to find the set of regions which violate the maximum via density rule after performing simultaneous redundant via insertion and line end extension. In the second stage, excess redundant vias are removed from those violating regions such that after the removal, the maximum via density rule is met while the total amount of redundant vias removed is minimized. This density-aware redundant via removal problem is formulated as a set of zero-one integer linear programming (0-1 ILP) problems each of which can be solved independently without sacrificing the optimality. The superiorities of our approaches are all demonstrated through promising experimental results.

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Cited By

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  • (2017)Redundant Via Insertion with Cut Optimization for Self-Aligned Double PatterningProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060440(137-142)Online publication date: 10-May-2017
  • (2016)MCFRoute 2.0Proceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902966(87-92)Online publication date: 18-May-2016
  • (2011)Simultaneous redundant via insertion and line end extension for yield optimizationProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950940(633-638)Online publication date: 25-Jan-2011
  • Show More Cited By

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cover image ACM Conferences
ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
November 2006
147 pages
ISBN:1595933891
DOI:10.1145/1233501
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 November 2006

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Cited By

View all
  • (2017)Redundant Via Insertion with Cut Optimization for Self-Aligned Double PatterningProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060440(137-142)Online publication date: 10-May-2017
  • (2016)MCFRoute 2.0Proceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902966(87-92)Online publication date: 18-May-2016
  • (2011)Simultaneous redundant via insertion and line end extension for yield optimizationProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950940(633-638)Online publication date: 25-Jan-2011
  • (2010)Redundant via Insertion: Removing Design Rule Conflicts and Balancing via DensityIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E93.A.2372E93-A:12(2372-2379)Online publication date: 2010
  • (2009)How to consider shorts and guarantee yield rate improvement for redundant wire insertionProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687407(33-38)Online publication date: 2-Nov-2009
  • (2009)Redundant via insertion with wire bendingProceedings of the 2009 international symposium on Physical design10.1145/1514932.1514960(123-130)Online publication date: 29-Mar-2009
  • (2008)Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyondProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356860(220-225)Online publication date: 21-Jan-2008
  • (2008)Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flowProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366195(359-362)Online publication date: 4-May-2008
  • (2008)Optimal post-routing redundant via insertionProceedings of the 2008 international symposium on Physical design10.1145/1353629.1353656(111-117)Online publication date: 13-Apr-2008

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