research-article

Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning

Authors:

Youngsoo ShinAuthors Info & Claims

GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

Pages 137 - 142

https://doi.org/10.1145/3060403.3060440

Published: 10 May 2017 Publication History

Abstract

Line-end cuts are employed to enable 1D gridded designs in self-aligned double patterning (SADP) process. Due to the minimum spacing constraints between adjacent cuts, cut optimization is important component. However, it brings a new challenge to redundant via (RV) insertion. As the cuts for RVs are not taken into account during line-end cut optimization, inserting some RVs may cause coloring conflicts or design rule violations.

In this paper, we address a combined RV insertion and cut optimization problem. Given a via layout, the proposed approach optimizes the cuts in upper and lower metal layers, which are connected through a via, while RV candidate positions are considered. Only the RV candidates that do not incur coloring conflicts and design rule violations are chosen. Our experiments indicate that only 55.3% of vias receive RVs when cut optimization and RV insertion are performed separately; corresponding number increases to 86.4% when our approach is applied.

References

[1]

K. Han et al., "ILP-based co-optimization of cut mask lay-out, dummy fill, and timing for sub-14nm BEOL technology," in Proc. SPIE Advanced Lithography, Oct. 2015, pp. 96 350E1--96 350E14.

[2]

M. Mirsaeedi, J. Torres, and M. Anis, "Self-aligned double patterning (SADP) layout decomposition," in Proc. Int. Symp. Qual. Electron. Des., Mar. 2011, pp. 1--7.

[3]

H. Zhang et al., "Mask cost reduction with circuit performance consideration for self-aligned double patterning," in Proc. Asia South Pacific Des. Autom. Conf., Jan. 2011, pp. 787--792.

Digital Library

[4]

Z. Xiao et al., "A polynomial time exact algorithm for overlay-resistant self-aligned double patterning (SADP) lay-out decomposition," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 32, no. 8, pp. 1228--1239, Aug. 2011.

Digital Library

[5]

J. Kuang, E. F. Young, and B. Yu, "Incorporating cut re- distribution with mask assignment to enable 1D gridded design," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2016, pp. 48--55.

Digital Library

[6]

S. Owa et al., "Immersion lithography extension to sub-10nm nodes with multiple patterning," in Proc. SPIE Advanced Lithography, Mar. 2014, pp. 90 520O1--90 520O9.

[7]

K.-Y. Lee, T.-C. Wang, and K.-Y. Chao, "Post-routing redundant via insertion and line end extension with via density consideration," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2006, pp. 633--640.

Digital Library

[8]

K.-Y. Lee and T.-C. Wang, "Post-routing redundant via insertion for yield/reliability improvement," in Proc. Asia South Pacific Des. Autom. Conf., Jan. 2006, pp. 303--308.

Digital Library

[9]

C.-K. Lei, P.-Y. Chiang, and Y.-M. Lee, "Post-routing redundant via insertion with wire spreading capability," in Proc. Asia South Pacific Des. Autom. Conf., Jan. 2009, pp. 468--473.

Digital Library

[10]

K.-Y. Lee et al., "Fast and optimal redundant via insertion," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 27, no. 12, pp. 2197--2208, Dec. 2008.

Digital Library

[11]

S.-Y. Fang, Y.-W. Chang, and W.-Y. Chen, "A novel lay-out decomposition algorithm for triple patterning lithography," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 33, no. 3, pp. 397--408, Feb. 2014.

Digital Library

[12]

Gurobi optimizer reference manual. {Online}. Available: http://www.gurobi.com

[13]

OpenCores. {Online}. Available: http://www.opencores.org

[14]

ITC99. {Online}. Available: http://www.cerc.utexas.edu/itc99-benchmarks/bench.html

[15]

"ISCAS89." {Online}. Available: http://www.cbl.ncsu.edu/benchmarks/ISCAS89/

[16]

R. Boppana and M. M. Halldórsson, "Approximating maximum independent sets by excluding subgraphs," BIT Nu- merical Mathematics, vol. 32, no. 2, pp. 180--196, Jun. 1992

Digital Library

Cited By

Song YJung JShin Y(2017)Redundant Via insertion in SADP process with cut merging and optimization2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2017.8203478(1-6)Online publication date: Oct-2017
https://doi.org/10.1109/VLSI-SoC.2017.8203478

Index Terms

Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Physical synthesis
      2. Wire routing

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Published In

cover image ACM Conferences

GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

May 2017

516 pages

ISBN:9781450349727

DOI:10.1145/3060403

General Chairs:
Laleh Behjat
University of Calgary, Canada
,
Jie Han
University of Alberta, Canada
,
Program Chairs:
Miroslav N. Velev
Aries Design Automation, USA
,
Deming Chen
University of Illinois, USA

Copyright © 2017 ACM.

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SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA
IEEE CASS

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 May 2017

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GLSVLSI '17: Great Lakes Symposium on VLSI 2017

May 10 - 12, 2017

Alberta, Banff, Canada

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GLSVLSI '17 Paper Acceptance Rate 48 of 197 submissions, 24%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Song YJung JShin Y(2017)Redundant Via insertion in SADP process with cut merging and optimization2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2017.8203478(1-6)Online publication date: Oct-2017
https://doi.org/10.1109/VLSI-SoC.2017.8203478

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