research-article

Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning

Authors:

Youngsoo ShinAuthors Info & Claims

GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

Pages 137 - 142

https://doi.org/10.1145/3060403.3060440

Published: 10 May 2017 Publication History

Abstract

Line-end cuts are employed to enable 1D gridded designs in self-aligned double patterning (SADP) process. Due to the minimum spacing constraints between adjacent cuts, cut optimization is important component. However, it brings a new challenge to redundant via (RV) insertion. As the cuts for RVs are not taken into account during line-end cut optimization, inserting some RVs may cause coloring conflicts or design rule violations.

In this paper, we address a combined RV insertion and cut optimization problem. Given a via layout, the proposed approach optimizes the cuts in upper and lower metal layers, which are connected through a via, while RV candidate positions are considered. Only the RV candidates that do not incur coloring conflicts and design rule violations are chosen. Our experiments indicate that only 55.3% of vias receive RVs when cut optimization and RV insertion are performed separately; corresponding number increases to 86.4% when our approach is applied.

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Cited By

Song YJung JShin Y(2017)Redundant Via insertion in SADP process with cut merging and optimization2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2017.8203478(1-6)Online publication date: Oct-2017
https://doi.org/10.1109/VLSI-SoC.2017.8203478

Index Terms

Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Physical synthesis
      2. Wire routing

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Published In

cover image ACM Conferences

GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

May 2017

516 pages

ISBN:9781450349727

DOI:10.1145/3060403

General Chairs:
Laleh Behjat
University of Calgary, Canada
,
Jie Han
University of Alberta, Canada
,
Program Chairs:
Miroslav N. Velev
Aries Design Automation, USA
,
Deming Chen
University of Illinois, USA

Copyright © 2017 ACM.

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SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA
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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 May 2017

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GLSVLSI '17: Great Lakes Symposium on VLSI 2017

May 10 - 12, 2017

Alberta, Banff, Canada

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GLSVLSI '17 Paper Acceptance Rate 48 of 197 submissions, 24%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Song YJung JShin Y(2017)Redundant Via insertion in SADP process with cut merging and optimization2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2017.8203478(1-6)Online publication date: Oct-2017
https://doi.org/10.1109/VLSI-SoC.2017.8203478

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