Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1109/ISCA45697.2020.00060acmconferencesArticle/Chapter ViewAbstractPublication PagesiscaConference Proceedingsconference-collections
research-article

Relaxed persist ordering using strand persistency

Published: 23 September 2020 Publication History

Abstract

Emerging persistent memory (PM) technologies promise the performance of DRAM with the durability of Flash. Several language-level persistency models have emerged recently to aid programming recoverable data structures in PM. Unfortunately, these persistency models are built upon hardware primitives that impose stricter ordering constraints on PM operations than the persistency models require. Alternative solutions use fixed and inflexible hardware logging techniques to relax ordering constraints on PM operations, but do not readily apply to general synchronization primitives employed by language-level persistency models. Instead, we propose StrandWeaver, a hardware strand persistency model, to minimally constrain ordering on PM operations. StrandWeaver manages PM order within a strand, a logically independent sequence of operations within a thread. PM operations that lie on separate strands are unordered and may drain concurrently to PM. StrandWeaver implements primitives under strand persistency to allow programmers to improve concurrency and relax ordering constraints on updates as they drain to PM. Furthermore, we design mechanisms that map persistency semantics in high-level language persistency models to the primitives implemented by StrandWeaver. We demonstrate that StrandWeaver can enable greater concurrency of PM operations than existing ISA-level ordering mechanisms, improving performance by up to 1.97x (1.45x avg.).

References

[1]
"INTEL OPTANE DC PERSISTENT MEMORY," https://www.intel.com/content/www/us/en/products/memory-storage/optane-dc-persistent-memory.html.
[2]
"Understand and deploy persistent memory," https://docs.microsoft.com/en-us/windows-server/storage/storage-spaces/deploy-pmem.
[3]
"Available first on Google Cloud: Intel Optane DC Persistent Memory," https://tinyurl.com/gcp-release.
[4]
M. Andrei, C. Lemke, G. Radestock, R. Schulze, C. Thiel, R. Blanco, A. Meghlan, M. Sharique, S. Seifert, S. Vishnoi, and et al., "Sap hana adoption of non-volatile memory," Proc. VLDB Endow., vol. 10, no. 12, p. 1754--1765, Aug. 2017.
[5]
"Instruction prefetching using branch prediction information," in Proceedings of the 1997 International Conference on Computer Design (ICCD '97), ser. ICCD '97. USA: IEEE Computer Society, 1997, p. 593.
[6]
J. Gray and A. Reuter, Transaction Processing: Concepts and Techniques, 1st ed. San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 1992.
[7]
D. E. Lowell and P. M. Chen, "Free transactions with rio vista," SIGOPS Oper. Syst. Rev., vol. 31, no. 5, p. 92--101, Oct. 1997.
[8]
C. Mohan, D. Haderle, B. Lindsay, H. Pirahesh, and P. Schwarz, "Aries: A transaction recovery method supporting fine-granularity locking and partial rollbacks using write-ahead logging," ACM Trans. Database Syst., vol. 17, no. 1, pp. 94--162, Mar. 1992.
[9]
Intel, "Intel architecture instruction set extensions programming reference (319433-022)," 2014, https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf.
[10]
ARM, "Armv8-a architecture evolution," 2016, https://tinyurl.com/arm-nvm.
[11]
D. R. Chakrabarti, H.-J. Boehm, and K. Bhandari, "Atlas: Leveraging locks for non-volatile memory consistency," in Proc. OOPSLA. New York, NY, USA: ACM, 2014, pp. 433--452.
[12]
V. Gogte, S. Diestelhorst, W. Wang, S. Narayanasamy, P. M. Chen, and T. F. Wenisch, "Persistency for synchronization-free regions," in Proc. PLDI. New York, NY, USA: ACM, 2018, pp. 46--61.
[13]
A. Kolli, V. Gogte, A. Saidi, S. Diestelhorst, P. M. Chen, S. Narayanasamy, and T. F. Wenisch, "Language-level persistency," in Proc. ISCA. New York, NY, USA: ACM, 2017, pp. 481--493.
[14]
A. Kolli, V. Gogte, A. Saidi, S. Diestelhorst, P. M. Chen, S. Narayanasamy, and T. F. Wenisch, "TARP: Translating acquire-release persistency," in NVMW, San Diego, CA, 2017. [Online]. Available: http://nvmw.eng.ucsd.edu/2017/assets/abstracts/1
[15]
V. Gogte, S. Diestelhorst, W. Wang, S. Narayanasamy, P. M. Chen, and T. F. Wenisch, "Failure-atomic synchronization-free regions," in NVMW, San Diego, CA, 2018. [Online]. Available: http://nvmw.ucsd.edu/nvmw18-program/unzip/current/nvmw2018-final42.pdf
[16]
S. Pelley, P. M. Chen, and T. F. Wenisch, "Memory persistency," SIGARCH Comput. Archit. News, vol. 42, no. 3, p. 265--276, Jun. 2014.
[17]
A. Kolli, J. Rosen, S. Diestelhorst, A. Saidi, S. Pelley, S. Liu, P. M. Chen, and T. F. Wenisch, "Delegated persist ordering," in Proc. MICRO. IEEE Press, 2016.
[18]
A. Joshi, V. Nagarajan, M. Cintra, and S. Viglas, "Efficient persist barriers for multicores," in Proc. MICRO. New York, NY, USA: ACM, 2015, pp. 660--671.
[19]
S. Nalli, S. Haria, M. D. Hill, M. M. Swift, H. Volos, and K. Keeton, "An analysis of persistent memory use with whisper," in Proc. ASPLOS. New York, NY, USA: ACM, 2017, pp. 135--148.
[20]
S. V. Adve and K. Gharachorloo, "Shared memory consistency models: A tutorial," Computer, vol. 29, no. 12, p. 66--76, Dec. 1996.
[21]
H.-J. Boehm and S. V. Adve, "Foundations of the c++ concurrency memory model," in Proc. PLDI. New York, NY, USA: ACM, 2008, pp. 68--78.
[22]
K. Gharachorloo, A. Gupta, and J. Hennessy, "Two techniques to enhance the performance of memory consistency models," in Proc. ICPC, 1991.
[23]
L. Lamport, "How to make a multiprocessor computer that correctly executes multiprocess programs," IEEE Trans. Comput., vol. 28, no. 9, p. 690--691, Sep. 1979.
[24]
D. Lustig, C. Trippel, M. Pellauer, and M. Martonosi, "Armor: Defending against memory consistency model mismatches in heterogeneous architectures," in Proc. ISCA. New York, NY, USA: Association for Computing Machinery, 2015, p. 388--400.
[25]
A. Kolli, S. Pelley, A. Saidi, P. M. Chen, and T. F. Wenisch, "High-performance transactions for persistent memories," in Proc. ASPLOS. New York, NY, USA: ACM, 2016, pp. 399--411.
[26]
J. Coburn, A. M. Caulfield, A. Akel, L. M. Grupp, R. K. Gupta, R. Jhala, and S. Swanson, "Nv-heaps: Making persistent objects fast and safe with next-generation, non-volatile memories," in Proc. ASPLOS. New York, NY, USA: ACM, 2011, pp. 105--118.
[27]
H. Volos, A. J. Tack, and M. M. Swift, "Mnemosyne: Lightweight persistent memory," in Proc. ASPLOS. New York, NY, USA: ACM, 2011, pp. 91--104.
[28]
J. Condit, E. B. Nightingale, C. Frost, E. Ipek, B. Lee, D. Burger, and D. Coetzee, "Better i/o through byte-addressable, persistent memory," in Proc. SOSP. New York, NY, USA: ACM, 2009, pp. 133--146.
[29]
"pmem.io: Persistent memory programming," https://pmem.io/pmdk/.
[30]
A. Kolli, V. Gogte, A. Saidi, S. Diestelhorst, W. Wang, P. M. Chen, S. Narayanasamy, and T. F. Wenisch, "Language support for memory persistency," IEEE Micro, vol. 39, no. 3, p. 94--102, May 2019.
[31]
M. Wu, Z. Zhao, H. Li, H. Li, H. Chen, B. Zang, and H. Guan, "Espresso: Brewing java for more non-volatility with non-volatile memory," in Proc. ASPLOS. New York, NY, USA: ACM, 2018, pp. 70--83.
[32]
J. Izraelevitz, H. Mendes, and M. L. Scott, "Linearizability of persistent memory objects under a full-system-crash failure model," in Proc. DISC. Berlin, Heidelberg: Springer Berlin Heidelberg, 2016, pp. 313--327.
[33]
A. Kolli, S. Pelley, A. Saidi, P. M. Chen, and T. F. Wenisch, "Persistency programming 101," in NVMW, San Diego, CA, 2015. [Online]. Available: http://nvmw.ucsd.edu/2015/assets/abstracts/33
[34]
A. Joshi, V. Nagarajan, S. Viglas, and M. Cintra, "Atom: Atomic durability in non-volatile memory through hardware logging," in Proc. HPCA, Feb 2017, pp. 361--372.
[35]
K. Doshi, E. Giles, and P. Varman, "Atomic persistence for scm with a non-intrusive backend controller," in Proc. HPCA, March 2016, pp. 77--89.
[36]
M. A. Ogleari, E. L. Miller, and J. Zhao, "Steal but no force: Efficient hardware undo+redo logging for persistent memory systems," in Proc. HPCA, Feb 2018, pp. 336--349.
[37]
A. Joshi, V. Nagarajan, M. Cintra, and S. Viglas, "Dhtm: Durable hardware transactional memory," in Proc. ISCA. IEEE Press, 2018, p. 452--465.
[38]
S. Shin, S. K. Tirukkovalluri, J. Tuck, and Y. Solihin, "Proteus: A flexible and fast software supported hardware logging approach for nvm," in Proc. MICRO. New York, NY, USA: ACM, 2017, pp. 178--190.
[39]
S. Owens, S. Sarkar, and P. Sewell, "A better x86 memory model: X86-tso," in Proc. TPHOLs. Berlin, Heidelberg: Springer-Verlag, 2009, pp. 391--407.
[40]
H.-J. Boehm and D. R. Chakrabarti, "Persistence programming models for non-volatile memory," in Proc. ISMM. New York, NY, USA: ACM, 2016, pp. 55--67.
[41]
T. Shull, J. Huang, and J. Torrellas, "Autopersist: An easy-to-use java nvm framework based on reachability," in Proc. PLDI. New York, NY, USA: ACM, 2019, pp. 316--332.
[42]
"Use Persistent Memory with Go," https://blogs.vmware.com/opensource/2019/04/03/persistent-memory-with-go/.
[43]
M. Liu, M. Zhang, K. Chen, X. Qian, Y. Wu, W. Zheng, and J. Ren, "Dudetm: Building durable transactions with decoupling for persistent memory," in Proc. ASPLOS. New York, NY, USA: ACM, 2017, pp. 329--343.
[44]
K. Bhandari, D. R. Chakrabarti, and H.-J. Boehm, "Implications of cpu caching on byte-addressable non-volatile memory programming," Hewlett-Packard, Tech. Rep. HPL-2012-236, December 2012.
[45]
S. Shin, J. Tuck, and Y. Solihin, "Hiding the long latency of persist barriers using speculative execution," in Proc. ISCA. New York, NY, USA: ACM, 2017, pp. 175--186.
[46]
Intel, "Deprecating the pcommit instruction," 2016, https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction.
[47]
D. M. Gallagher, W. Y. Chen, S. A. Mahlke, J. C. Gyllenhaal, and W.-m. W. Hwu, "Dynamic memory disambiguation using the memory conflict buffer," in Proc. ASPLOS. New York, NY, USA: ACM, 1994, pp. 183--193.
[48]
R. Ghiya, D. Lavery, and D. Sehr, "On the importance of points-to analysis and other memory disambiguation methods for c programs," in Proc. PLDI. New York, NY, USA: ACM, 2001, pp. 47--58.
[49]
S. Sethumadhavan, R. Desikan, D. Burger, C. R. Moore, and S. W. Keckler, "Scalable hardware memory disambiguation for high ilp processors," in Proc. MICRO. Washington, DC, USA: IEEE Computer Society, 2003, pp. 399--.
[50]
W. Wang and S. Diestelhorst, "Quantify the performance overheads of pmdk," in Proc. MEMSYS. New York, NY, USA: ACM, 2018, pp. 50--52.
[51]
A. Arvind and J.-W. Maessen, "Memory model = instruction reordering + store atomicity," in Proc. ISCA. USA: IEEE Computer Society, 2006, p. 29--40.
[52]
L. Lamport, "Time, clocks, and the ordering of events in a distributed system," Commun. ACM, vol. 21, no. 7, p. 558--565, Jul. 1978.
[53]
M. Batty, S. Owens, S. Sarkar, P. Sewell, and T. Weber, "Mathematizing C++ concurrency," in Proc. POPL. New York, NY, USA: ACM, 2011, pp. 55--66.
[54]
"C++ bindings for libpmemobj - synchronization primitives," http://pmem.io/2016/05/31/cpp-08.html.
[55]
C. Blundell, M. M. Martin, and T. F. Wenisch, "Invisifence: performance-transparent memory ordering in conventional multiprocessors," in ACM SIGARCH Computer Architecture News, vol. 37, no. 3. ACM, 2009, pp. 233--244.
[56]
T. F. Wenisch, A. Ailamaki, B. Falsafi, and A. Moshovos, "Mechanisms for store-wait-free multiprocessors," SIGARCH Comput. Archit. News, vol. 35, no. 2, p. 266--277, Jun. 2007.
[57]
Intel, "Persistent memory programming," 2015, http://pmem.io/.
[58]
J. Izraelevitz, J. Yang, L. Zhang, J. Kim, X. Liu, A. Memaripour, Y. J. Soh, Z. Wang, Y. Xu, S. R. Dulloor, J. Zhao, and S. Swanson, "Basic performance measurements of the intel optane DC persistent memory module," CoRR, vol. abs/1903.05714, 2019. [Online]. Available: http://arxiv.org/abs/1903.05714
[59]
N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, and et al., "The gem5 simulator," SIGARCH Comput. Archit. News, vol. 39, no. 2, p. 1--7, Aug. 2011.
[60]
J. Arulraj, A. Pavlo, and S. R. Dulloor, "Let's talk about storage & recovery methods for non-volatile memory database systems," in Proc. SIGMOD. New York, NY, USA: ACM, 2015, pp. 707--722.
[61]
T. P. P. C. (TPC), "Tpc benchmark b," 2010, http://www.tpc.org/tpc_documents_current_versions/pdf/tpc-c_v5-11.pdf.
[62]
J. Zhao, S. Li, D. H. Yoon, Y. Xie, and N. P. Jouppi, "Kiln: Closing the performance gap between systems with and without persistence support," in Proc. MICRO. New York, NY, USA: ACM, 2013, pp. 421--432.
[63]
D. Gope, A. Basu, S. Puthoor, and M. Meswani, "A case for scoped persist barriers in gpus," in Proc. GPGPU. New York, NY, USA: ACM, 2018, pp. 2--12.
[64]
X. Wu and A. L. N. Reddy, "Scmfs: A file system for storage class memory," in Prof. SC, ser. SC '11. New York, NY, USA: Association for Computing Machinery, 2011.
[65]
H. Volos, S. Nalli, S. Panneerselvam, V. Varadarajan, P. Saxena, and M. M. Swift, "Aerie: Flexible file-system interfaces to storage-class memory," in Proc. EuroSys. New York, NY, USA: ACM, 2014, pp. 14:1--14:14.
[66]
J. Xu and S. Swanson, "Nova: A log-structured file system for hybrid volatile/non-volatile main memories," in Proc. FAST. USA: USENIX Association, 2016, p. 323--338.
[67]
J. Xu, L. Zhang, A. Memaripour, A. Gangadharaiah, A. Borase, T. B. Da Silva, S. Swanson, and A. Rudoff, "Nova-fortis: A fault-tolerant non-volatile main memory file system," in Proc. SOSP. New York, NY, USA: ACM, 2017, pp. 478--496.
[68]
S. R. Dulloor, S. Kumar, A. Keshavamurthy, P. Lantz, D. Reddy, R. Sankaran, and J. Jackson, "System software for persistent memory," in Proc. EuroSys. New York, NY, USA: ACM, 2014, pp. 15:1--15:15.
[69]
J. Xu, J. Kim, A. Memaripour, and S. Swanson, "Finding and fixing performance pathologies in persistent memory software stacks," in Proc. ASPLOS. New York, NY, USA: ACM, 2019, pp. 427--439.
[70]
T. Wang and R. Johnson, "Scalable logging through emerging non-volatile memory," Proc. VLDB Endow., vol. 7, no. 10, p. 865--876, Jun. 2014.
[71]
A. Chatzistergiou, M. Cintra, and S. D. Viglas, "REWIND: recovery write-ahead system for in-memory non-volatile data-structures," Proc. VLDB Endow., vol. 8, no. 5, p. 497--508, Jan. 2015.
[72]
I. Oukid, D. Booss, W. Lehner, P. Bumbulis, and T. Willhalm, "Sofort: A hybrid scm-dram storage engine for fast data recovery," in Proc. DaMoN, 2014.
[73]
H. Kimura, "Foedus: Oltp engine for a thousand cores and nvram," in Proc. SIGMOD. New York, NY, USA: Association for Computing Machinery, 2015, p. 691--706.
[74]
J. Arulraj, M. Perron, and A. Pavlo, "Write-behind logging," Proc. VLDB Endow., vol. 10, no. 4, p. 337--348, Nov. 2016.
[75]
A. Memaripour, A. Badam, A. Phanishayee, Y. Zhou, R. Alagappan, K. Strauss, and S. Swanson, "Atomic in-place updates for non-volatile main memories with kamino-tx," in Proc. EuroSys. New York, NY, USA: ACM, 2017, pp. 499--512.
[76]
J. Guerra, L. Marmol, D. Campello, C. Crespo, R. Rangaswami, and J. Wei, "Software persistent memory," in Proc. ATC. Boston, MA: USENIX, 2012, pp. 319--331.
[77]
T. M. Nguyen and D. Wentzlaff, "Picl: A software-transparent, persistent cache log for nonvolatile main memory," in Proc. MICRO. IEEE Press, 2018, p. 507--519.
[78]
V. Gogte, W. Wang, S. Diestelhorst, A. Kolli, P. M. Chen, S. Narayanasamy, and T. F. Wenisch, "Software wear management for persistent memories," in Proc. FAST. Boston, MA: USENIX Association, Feb. 2019, pp. 45--63.
[79]
I. Narayanan, A. Ganesan, A. Badam, S. Govindan, B. Sharma, and A. Sivasubramaniam, "Getting more performance with polymorphism from emerging memory technologies," in Proc. SYSTOR. New York, NY, USA: ACM, 2019, pp. 8--20.
[80]
J. Huang, K. Schwan, and M. K. Qureshi, "Nvram-aware logging in transaction systems," Proc. VLDB Endow., vol. 8, no. 4, p. 389--400, Dec. 2014.
[81]
H.-J. Boehm and D. R. Chakrabarti, "Persistence programming models for non-volatile memory," in Proc. ISMM. New York, NY, USA: ACM, 2016, pp. 55--67.
[82]
S. Venkataraman, N. Tolia, P. Ranganathan, and R. H. Campbell, "Consistent and durable data structures for non-volatile byte-addressable memory," in Proc. FAST. Berkeley, CA, USA: USENIX Association, 2011, pp. 5--5.
[83]
F. Nawab, D. Chakrabarti, T. Kelly, and C. B. M. III, "Procrastination beats prevention: Timely sufficient persistence for efficient crash resilience," Hewlett-Packard, Tech. Rep. HPL-2014-70, December 2014.
[84]
D. Hwang, W.-H. Kim, Y. Won, and B. Nam, "Endurable transient inconsistency in byte-addressable persistent b+-tree," in Proc. FAST. Oakland, CA: USENIX Association, 2018, pp. 187--200.
[85]
H. Chauhan, I. Calciu, V. Chidambaram, E. Schkufza, O. Mutlu, and P. Subrahmanyam, "NVMOVE: Helping programmers move to byte-based persistence," in INFLOW. Savannah, GA: USENIX Association, Nov. 2016.
[86]
D. Kim, A. Memaripour, A. Badam, Y. Zhu, H. H. Liu, J. Padhye, S. Raindel, S. Swanson, V. Sekar, and S. Seshan, "Hyperloop: Group-based nic-offloading to accelerate replicated transactions in multi-tenant storage systems," in Proc. SIGCOMM. New York, NY, USA: ACM, 2018, pp. 297--312.
[87]
Y. Zhang, J. Yang, A. Memaripour, and S. Swanson, "Mojim: A reliable and highly-available non-volatile memory system," in Proc. ASPLOS. New York, NY, USA: ACM, 2015, pp. 3--18.
[88]
Y. Zhou, R. Alagappan, A. Memaripour, A. Badam, and D. Wentzlaff, "Hnvm: Hybrid nvm enabled datacenter design and optimization," Microsoft, Microsoft Research, Tech. Rep. MSR-TR-2017-8, 2017.
[89]
Y. Lu, J. Shu, Y. Chen, and T. Li, "Octopus: an rdma-enabled distributed persistent memory file system," in Proc. ATC. Santa Clara, CA: USENIX Association, 2017, pp. 773--785.
[90]
C. Xu, D. Niu, N. Muralimanohar, R. Balasubramonian, T. Zhang, S. Yu, and Y. Xie, "Overcoming the challenges of crossbar resistive memory architectures," in Proc. HPCA, Feb 2015, pp. 476--488.
[91]
E. R. Giles, K. Doshi, and P. Varman, "Softwrap: A lightweight framework for transactional support of storage class memory," in 2015 31st Symposium on Mass Storage Systems and Technologies (MSST), May 2015, pp. 1--14.
[92]
J. Gu, Q. Yu, X. Wang, Z. Wang, B. Zang, H. Guan, and H. Chen, "Pisces: A scalable and efficient persistent transactional memory," in Proc. ATC. Renton, WA: USENIX Association, Jul. 2019, pp. 913--928.
[93]
T. Wang, S. Sambasivam, Y. Solihin, and J. Tuck, "Hardware supported persistent object address translation," in Proc. MICRO. New York, NY, USA: ACM, 2017, pp. 800--812.
[94]
T. C.-H. Hsu, H. Brügner, I. Roy, K. Keeton, and P. Eugster, "Nvthreads: Practical persistence for multi-threaded applications," in Proc. EuroSys. New York, NY, USA: Association for Computing Machinery, 2017, p. 468--482.
[95]
J. Izraelevitz, T. Kelly, and A. Kolli, "Failure-atomic persistent memory updates via justdo logging," in Proc. ASPLOS. New York, NY, USA: ACM, 2016, pp. 427--442.
[96]
S. Liu, K. Seemakhupt, G. Pekhimenko, A. Kolli, and S. Khan, "Janus: Optimizing memory and storage support for non-volatile memory systems," in Proc. ISCA. New York, NY, USA: ACM, 2019, pp. 143--156.
[97]
K. Maeng, A. Colin, and B. Lucia, "Alpaca: Intermittent execution without checkpoints," Proc. ACM Program. Lang., vol. 1, no. OOPSLA, Oct. 2017.
[98]
E. Ruppel and B. Lucia, "Transactional concurrency control for intermittent, energy-harvesting computing systems," in Proc. PLDI. New York, NY, USA: ACM, 2019, pp. 1085--1100.
[99]
C. Lin, V. Nagarajan, and R. Gupta, "Fence scoping," in Proc. SC, ser. SC '14. IEEE Press, 2014, p. 105--116.
[100]
A. Mirhoseini, E. M. Songhori, and F. Koushanfar, "Idetic: A high-level synthesis approach for enabling long computations on transiently-powered asics," in Proc. PerCom, March 2013, pp. 216--224.
[101]
D. Balsamo, A. S. Weddell, A. Das, A. R. Arreola, D. Brunelli, B. M. Al-Hashimi, G. V. Merrett, and L. Benini, "Hibernus++: A self-calibrating and adaptive system for transiently-powered embedded devices," Trans. CAD, vol. 35, no. 12, p. 1968--1980, Nov. 2016.
[102]
A. Mirhosseini, A. Agrawal, and J. Torrellas, "Survive: Pointer-based in-dram incremental checkpointing for low-cost data persistence and rollback-recovery," IEEE Computer Architecture Letters, vol. 16, no. 2, pp. 153--157, July 2017.
[103]
S. Kannan, A. Gavrilovska, K. Schwan, and D. Milojicic, "Optimizing checkpoints using nvm as virtual memory," in Proc. IPDPS. USA: IEEE Computer Society, 2013, p. 29--40.
[104]
J. Ren, J. Zhao, S. Khan, J. Choi, Y. Wu, and O. Mutlu, "Thynvm: Enabling software-transparent crash consistency in persistent memory systems," in Proc. MICRO. New York, NY, USA: ACM, 2015, pp. 672--685.
[105]
B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, "Architecting phase change memory as a scalable dram alternative," in Proc. ISCA. New York, NY, USA: ACM, 2009, pp. 2--13.
[106]
S. Kannan, A. Gavrilovska, and K. Schwan, "pvm: Persistent virtual memory for efficient capacity scaling and object storage," in Proc. EuroSys. New York, NY, USA: ACM, 2016, pp. 13:1--13:16.
[107]
M. K. Qureshi, V. Srinivasan, and J. A. Rivers, "Scalable high performance main memory system using phase-change memory technology," in Proc. ISCA. New York, NY, USA: ACM, 2009, pp. 24--33.
[108]
M. K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali, "Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling," in Proc. MICRO. New York, NY, USA: ACM, 2009, pp. 14--23.

Cited By

View all
  • (2023)Scoped Buffered Persistency Model for GPUsProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3575693.3575749(688-701)Online publication date: 27-Jan-2023
  • (2023)Chipmunk: Investigating Crash-Consistency in Persistent-Memory File SystemsProceedings of the Eighteenth European Conference on Computer Systems10.1145/3552326.3567498(718-733)Online publication date: 8-May-2023
  • (2022)Achieving crash consistency by employing persistent L1 cacheProceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe10.5555/3539845.3540172(1407-1412)Online publication date: 14-Mar-2022
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
ISCA '20: Proceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture
May 2020
1152 pages
ISBN:9781728146614

Sponsors

In-Cooperation

  • IEEE

Publisher

IEEE Press

Publication History

Published: 23 September 2020

Check for updates

Author Tags

  1. failure atomicity
  2. language memory models
  3. memory persistency
  4. persistent memories
  5. strand persistency

Qualifiers

  • Research-article

Conference

ISCA '20
Sponsor:

Acceptance Rates

Overall Acceptance Rate 543 of 3,203 submissions, 17%

Upcoming Conference

ISCA '25

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)8
  • Downloads (Last 6 weeks)0
Reflects downloads up to 19 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2023)Scoped Buffered Persistency Model for GPUsProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3575693.3575749(688-701)Online publication date: 27-Jan-2023
  • (2023)Chipmunk: Investigating Crash-Consistency in Persistent-Memory File SystemsProceedings of the Eighteenth European Conference on Computer Systems10.1145/3552326.3567498(718-733)Online publication date: 8-May-2023
  • (2022)Achieving crash consistency by employing persistent L1 cacheProceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe10.5555/3539845.3540172(1407-1412)Online publication date: 14-Mar-2022
  • (2022)Checking robustness to weak persistency modelsProceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation10.1145/3519939.3523723(490-505)Online publication date: 9-Jun-2022
  • (2022)Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal storesProceedings of the ACM on Programming Languages10.1145/34986836:POPL(1-31)Online publication date: 12-Jan-2022
  • (2021)COSPlay: Leveraging Task-Level Parallelism for High-Throughput Synchronous PersistenceMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480075(86-99)Online publication date: 18-Oct-2021
  • (2021)Distributed Data PersistencyMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480060(71-85)Online publication date: 18-Oct-2021
  • (2021)Execution dependence extension (EDE)Proceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00043(456-469)Online publication date: 14-Jun-2021

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media