Article

Formal Verification of Pipelined Microprocessors with Delayed Branches

Author:

Miroslav N. VelevAuthors Info & Claims

ISQED '06: Proceedings of the 7th International Symposium on Quality Electronic Design

Pages 296 - 299

https://doi.org/10.1109/ISQED.2006.68

Published: 27 March 2006 Publication History

Abstract

Presented is an approach for formal verification of pipelined microprocessors with delayed branches, i.e., branch instructions whose immediately following instruction is always executed regardless of whether the branch is taken. Delayed branches are used in the instruction sets of the MIPS, SPARC, and PA-RISC architectures. Because of their sequential semantics that spans several consecutive instruction slots, delayed branches complicate the checking of safety and liveness for pipelined designs. The presented approach is highly automatic compared to previous methods for formal verification of pipelined processors with delayed branches.

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Cited By

Velev MGao P(2011)Exploiting abstraction for efficient formal verification of DSPs with arrays of reconfigurable functional unitsProceedings of the 13th international conference on Formal methods and software engineering10.5555/2075089.2075117(307-322)Online publication date: 26-Oct-2011
https://dl.acm.org/doi/10.5555/2075089.2075117
Kühne UBeyer SBormann JBarstow JBloem RSharygina N(2010)Automated formal verification of processors based on architectural modelsProceedings of the 2010 Conference on Formal Methods in Computer-Aided Design10.5555/1998496.1998521(129-136)Online publication date: 20-Oct-2010
https://dl.acm.org/doi/10.5555/1998496.1998521

Index Terms

Formal Verification of Pipelined Microprocessors with Delayed Branches

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cover image ACM Conferences

ISQED '06: Proceedings of the 7th International Symposium on Quality Electronic Design

March 2006

787 pages

ISBN:0769525237

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SIGDA: ACM Special Interest Group on Design Automation

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IEEE Computer Society

United States

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Published: 27 March 2006

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Cited By

Velev MGao P(2011)Exploiting abstraction for efficient formal verification of DSPs with arrays of reconfigurable functional unitsProceedings of the 13th international conference on Formal methods and software engineering10.5555/2075089.2075117(307-322)Online publication date: 26-Oct-2011
https://dl.acm.org/doi/10.5555/2075089.2075117
Kühne UBeyer SBormann JBarstow JBloem RSharygina N(2010)Automated formal verification of processors based on architectural modelsProceedings of the 2010 Conference on Formal Methods in Computer-Aided Design10.5555/1998496.1998521(129-136)Online publication date: 20-Oct-2010
https://dl.acm.org/doi/10.5555/1998496.1998521

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