A Low Power TLB Structure for Embedded Systems

Power consumption and power density for the Translation Look-aside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as well. After pointing out the importance of instruction TLB (iTLB) power ...

Translation Lookaside Buffers (TLBs) are critical to overall system performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as Chip MultiProcessors (CMPs) become ubiquitous, TLB design and ...

This paper proposes an efficient cache scheme to reduce power consumption and conflict misses for single-core or multi-core embedded computing architecture. The proposed cache requires an additional gate stage before it accesses the cache line, which ...