Article

Compiler-directed code restructuring for reducing data TLB energy

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G. ChenAuthors Info & Claims

CODES+ISSS '04: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 98 - 103

https://doi.org/10.1145/1016720.1016747

Published: 08 September 2004 Publication History

Abstract

Prior work on TLB power optimization considered circuit and architectural techniques. A recent software-based technique for data TLBs has considered the possibility of storing the frequently used virtual-to-physical address translations in a set of translation registers (TRs), and using them when necessary instead of going to the data TLB. This paper presents a compiler-based strategy for increasing the effectiveness of TRs. The idea is to restructure the application code in such a fashion that once a TR is loaded, its contents are reused as much as possible. Our experimental evaluation with six array-based benchmarks from the Spec2000 suite indicates that the proposed TR reuse strategy brings significant reductions in data TLB energy over an alternate strategy that employs TRs but does not restructure the code for TR reuse.

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Cited By

Varma KPatil GRaveendran B(2017)DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.50(207-212)Online publication date: Jan-2017
https://doi.org/10.1109/VLSID.2017.50
Karakostas VGandhi JCristal AHill MMcKinley KNemirovsky MSwift MUnsal O(2016)Energy-efficient address translation2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446100(631-643)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446100
Mittal S(2016)A survey of techniques for architecting TLBsConcurrency and Computation: Practice and Experience10.1002/cpe.406129:10Online publication date: 22-Dec-2016
https://doi.org/10.1002/cpe.4061
Show More Cited By

Index Terms

Compiler-directed code restructuring for reducing data TLB energy
1. Software and its engineering
  1. Software notations and tools
    1. Compilers

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cover image ACM Conferences

CODES+ISSS '04: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

September 2004

266 pages

ISBN:158113 9373

DOI:10.1145/1016720

General Chairs:
Alex Orailoglu
University of California, San Diego, CA
,
Pai H. Chou
University of California, Irvine, CA
,
Program Chairs:
Petru Eles
Linköping University, Sweden
,
Axel Jantsch
Royal Institute of Technology, Sweden

Copyright © 2004 ACM.

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Published: 08 September 2004

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CODES/ISSS04: Second IEEE/ACM/IFIP International CODES/ ISSS 2004 Merged Conference

September 8 - 10, 2004

Stockholm, Sweden

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Cited By

Varma KPatil GRaveendran B(2017)DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.50(207-212)Online publication date: Jan-2017
https://doi.org/10.1109/VLSID.2017.50
Karakostas VGandhi JCristal AHill MMcKinley KNemirovsky MSwift MUnsal O(2016)Energy-efficient address translation2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446100(631-643)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446100
Mittal S(2016)A survey of techniques for architecting TLBsConcurrency and Computation: Practice and Experience10.1002/cpe.406129:10Online publication date: 22-Dec-2016
https://doi.org/10.1002/cpe.4061
Meenderinck CMolnos AGoossens K(2012)Composable Virtual Memory for an Embedded SoCProceedings of the 2012 15th Euromicro Conference on Digital System Design10.1109/DSD.2012.32(766-773)Online publication date: 5-Sep-2012
https://dl.acm.org/doi/10.1109/DSD.2012.32
Zhou XPetrov P(2011)Towards virtual memory support in real-time and memory-constrained embedded applications: the interval page tableIET Computers & Digital Techniques10.1049/iet-cdt.2009.00305:4(287)Online publication date: 2011
https://doi.org/10.1049/iet-cdt.2009.0030
Chukhman IPetrov PBahar RLombardi FAtienza DBrunvand E(2010)Context-aware TLB preloading for interference reduction in embedded multi-tasked systemsProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785574(401-404)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785574
Jeyapaul RShrivastava A(2010)Code Transformations for TLB Power ReductionInternational Journal of Parallel Programming10.1007/s10766-009-0123-838:3-4(254-276)Online publication date: 21-Jan-2010
https://doi.org/10.1007/s10766-009-0123-8
Zhou XPetrov P(2009)Direct address translation for virtual memory in energy-efficient embedded systemsACM Transactions on Embedded Computing Systems10.1145/1457246.14572518:1(1-31)Online publication date: 4-Jan-2009
https://dl.acm.org/doi/10.1145/1457246.1457251
Zhou XPetrov P(2008)Heterogeneously tagged caches for low-power embedded systems with virtual memory supportACM Transactions on Design Automation of Electronic Systems10.1145/1344418.134442813:2(1-24)Online publication date: 23-Apr-2008
https://dl.acm.org/doi/10.1145/1344418.1344428
Zhou XPetrov P(2008)Low-power and real-time address translation through arithmetic operations for virtual memory support in embedded systemsIET Computers & Digital Techniques10.1049/iet-cdt:200700902:2(75)Online publication date: 2008
https://doi.org/10.1049/iet-cdt:20070090
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