poster

Context-aware TLB preloading for interference reduction in embedded multi-tasked systems

Authors:

Ilya Chukhman,

Peter PetrovAuthors Info & Claims

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI

Pages 401 - 404

https://doi.org/10.1145/1785481.1785574

Published: 16 May 2010 Publication History

Get Access

Abstract

Rapid system responsiveness and execution time predictability are of significant importance for a large class of real-time embedded systems. Multi-tasking leads to interference in the shared processor resources such as caches and TLBs, which in turn results in not only deteriorated performance but also, and for some applications even more importantly, highly suboptimal worst-case execution time (WCET) estimates due to the interference unpredictability. We present a methodology for task-aware D-TLB interference reduction and preloading through an application-specific task's state introspection at context-switch time for embedded multitasking. The proposed technique addresses the problem through a synergistic cooperation between the compiler, for an application-specific analysis of the task's context, and the OS, for a run-time introspection of the context and an efficient identification of TLB entries of current (live) and of "near-future" usage.

References

[1]

B. Jacob, S. Ng and D. Wang, Memory Systems: Cache, DRAM, Disk, Morgan Kaufmann, 2007.

Digital Library

Google Scholar

[2]

A. Agarwal, J. Hennessy and M. Horowitz, "Cache performance of operating system and multiprogramming workloads", ACM Transactions on Computer Systems, vol. 6, n. 4, pp. 393--431, 1988.

Digital Library

Google Scholar

[3]

S. Yamada and S. Kusakabe, "Effect of context aware scheduler on TLB", in International Symposium on Parallel and Distributed Processing (IPDPS), pp. 1--8, April 2008.

Google Scholar

[4]

Isabelle Puaut and Damien Hardy, "Predictable Paging in Real-Time Systems: A Compiler Approach", in Euromicro Conference on Real-Time Systems (ECRTS), pp. 169--178, 2007.

Digital Library

Google Scholar

[5]

R. Heckmann, M. Langenbach, S. Thesing and R. Wilhelm, "The influence of processor architecture on the design and the results of WCET tools", Proceedings of the IEEE, vol. 91, n. 7, pp. 1038--1054, July 2003.

Crossref

Google Scholar

[6]

J. Staschulat and R. Ernst, "Worst case timing analysis of input dependent data cache behavior", in Euromicro Conference on Real-Time Systems (ECRTS), pp. 227--236, 2006.

Digital Library

Google Scholar

[7]

M. Kandemir, I. Kadayif and G. Chen, "Compiler-Directed Code Restructuring for Reducing Data TLB Energy", in CODES ISSS, pp. 98--103, Sept. 2004.

Digital Library

Google Scholar

[8]

Ashley Saulsbury, Fredrik Dahlgren and Per Stenström, "Recency-based TLB preloading", in International Symposium on Computer Architecture (ISCA), pp. 117--127, New York, NY, USA, 2000, ACM.

Digital Library

Google Scholar

[9]

Gokul B. Kandiraju and Anand Sivasubramaniam, "Going the distance for TLB prefetching: an application-driven study", in International Symposium on Computer Architecture (ISCA), pp. 195--206, 2002.

Digital Library

Google Scholar

[10]

T. Austin, E. Larson and D. Ernst, "SimpleScalar: An infrastructure for computer system modeling", IEEE Computer, vol. 35, n. 2, pp. 59--67, Feb. 2002.

Digital Library

Google Scholar

Cited By

View all

Li ASudvarg MLiu HYu ZGill CZhang N(2022)PolyRhythm: Adaptive Tuning of a Multi-Channel Attack Template for Timing Interference2022 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS55097.2022.00028(225-239)Online publication date: Dec-2022
https://doi.org/10.1109/RTSS55097.2022.00028
Varma KPatil GRaveendran B(2017)DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.50(207-212)Online publication date: Jan-2017
https://doi.org/10.1109/VLSID.2017.50
Mittal S(2016)A survey of techniques for architecting TLBsConcurrency and Computation: Practice and Experience10.1002/cpe.406129:10Online publication date: 22-Dec-2016
https://doi.org/10.1002/cpe.4061

Index Terms

Context-aware TLB preloading for interference reduction in embedded multi-tasked systems
1. Computer systems organization
  1. Architectures
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory

Recommendations

Morrigan: A Composite Instruction TLB Prefetcher
MICRO '21: MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture

The effort to reduce address translation overheads has typically targeted data accesses since they constitute the overwhelming portion of the second-level TLB (STLB) misses in desktop and HPC applications. The address translation cost of instruction ...
TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs

Translation Lookaside Buffers (TLBs) are critical to overall system performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as Chip MultiProcessors (CMPs) become ubiquitous, TLB design and ...
Going the distance for TLB prefetching: an application-driven study
Special Issue: Proceedings of the 29th annual international symposium on Computer architecture (ISCA '02)

The importance of the Translation Lookaside Buffer (TLB) on system performance is well known. There have been numerous prior efforts addressing TLB design issues for cutting down access times and lowering miss rates. However, it was only recently that ...

Comments

Information & Contributors

Information

Published In

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI

May 2010

502 pages

ISBN:9781450300124

DOI:10.1145/1785481

General Chairs:
R. Iris Bahar
Brown University, USA
,
Fabrizio Lombardi
Northeastern University, USA
,
Program Chairs:
David Atienza
EPFL, Switzerland
,
Erik Brunvand
University of Utah, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

IEEE CEDA
IEEE CASS

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 May 2010

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Poster

Conference

GLSVLSI '10

Sponsor:

SIGDA

GLSVLSI '10: Great Lakes Symposium on VLSI 2010

May 16 - 18, 2010

Rhode Island, Providence, USA

Acceptance Rates

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
179
Total Downloads

Downloads (Last 12 months)9
Downloads (Last 6 weeks)1

Reflects downloads up to 12 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Li ASudvarg MLiu HYu ZGill CZhang N(2022)PolyRhythm: Adaptive Tuning of a Multi-Channel Attack Template for Timing Interference2022 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS55097.2022.00028(225-239)Online publication date: Dec-2022
https://doi.org/10.1109/RTSS55097.2022.00028
Varma KPatil GRaveendran B(2017)DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.50(207-212)Online publication date: Jan-2017
https://doi.org/10.1109/VLSID.2017.50
Mittal S(2016)A survey of techniques for architecting TLBsConcurrency and Computation: Practice and Experience10.1002/cpe.406129:10Online publication date: 22-Dec-2016
https://doi.org/10.1002/cpe.4061

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Morrigan: A Composite Instruction TLB Prefetcher

TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs

Going the distance for TLB prefetching: an application-driven study