research-article

Scaling to the End of Silicon with EDGE Architectures

Authors:

Stephen W. Keckler,

Kathryn S. McKinley,

Charles R. Moore,

Robert G. McDonald,

the TRIPS TeamAuthors Info & Claims

Computer, Volume 37, Issue 7

Pages 44 - 55

https://doi.org/10.1109/MC.2004.65

Published: 01 July 2004 Publication History

Abstract

Post-RISC microprocessor designs must introduce new ISAs to address the challenges that modern CMOS technologies pose while also exploiting the massive levels of integration now possible. To meet these challenges, the TRIPS Team at the University of Texas at Austin has developed a new class of ISAs, called Explicit Data Graph Execution, that will match the characteristics of semiconductor technology over the next decade.EDGE architectures appear to offer a progressively better solution as technology scales down to the end of silicon, with each generation providing a richer spatial substrate at the expense of increased global communication delays.

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Cited By

Elakhras AGuerrieri AJosipovic LIenne PZhang ZPutnam A(2024)Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow CircuitsProceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3626202.3637556(44-54)Online publication date: 1-Apr-2024
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Koizumi TShioya RSugita SAmano TDegawa YKadomoto JIrie HSakai S(2023)Clockhands: Rename-free Instruction Set Architecture for Out-of-order ProcessorsProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614272(1-16)Online publication date: 28-Oct-2023
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Bhagyanath AKercher NSchneider KZhu Qvon Hanxleden RStephen EBrandt J(2023)Allocation and Scheduling of Dataflow Graphs on Hybrid Dataflow/von Neumann ArchitecturesProceedings of the 21st ACM-IEEE International Conference on Formal Methods and Models for System Design10.1145/3610579.3611079(59-70)Online publication date: 21-Sep-2023
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Index Terms

Scaling to the End of Silicon with EDGE Architectures
1. Hardware
  1. Integrated circuits
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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Published In

cover image Computer

Computer Volume 37, Issue 7

July 2004

84 pages

ISSN:0018-9162

Issue’s Table of Contents

Copyright © 2004.

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 July 2004

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Cited By

Elakhras AGuerrieri AJosipovic LIenne PZhang ZPutnam A(2024)Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow CircuitsProceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3626202.3637556(44-54)Online publication date: 1-Apr-2024
https://dl.acm.org/doi/10.1145/3626202.3637556
Koizumi TShioya RSugita SAmano TDegawa YKadomoto JIrie HSakai S(2023)Clockhands: Rename-free Instruction Set Architecture for Out-of-order ProcessorsProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614272(1-16)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614272
Bhagyanath AKercher NSchneider KZhu Qvon Hanxleden RStephen EBrandt J(2023)Allocation and Scheduling of Dataflow Graphs on Hybrid Dataflow/von Neumann ArchitecturesProceedings of the 21st ACM-IEEE International Conference on Formal Methods and Models for System Design10.1145/3610579.3611079(59-70)Online publication date: 21-Sep-2023
https://dl.acm.org/doi/10.1145/3610579.3611079
Schneider KBhagyanath A(2023)Consistency Constraints for Mapping Dataflow Graphs to Hybrid Dataflow/von Neumann ArchitecturesACM Transactions on Embedded Computing Systems10.1145/360786922:5(1-25)Online publication date: 26-Sep-2023
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Schneider KArun-Kumar SMery DSaha IZhang L(2021)Translating structured sequential programs to dataflow graphsProceedings of the 19th ACM-IEEE International Conference on Formal Methods and Models for System Design10.1145/3487212.3487343(66-77)Online publication date: 20-Nov-2021
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