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research-article

Proteus: An ASIC Flow for GHz Asynchronous Designs

Published: 01 September 2011 Publication History

Abstract

Editors' note:The high-performance benefits of asynchronous design have hitherto been obtained only using full-custom design. This article presents an industrial-strength asynchronous ASIC CAD flow that enables the automatic synthesis and physical design of high-level specifications into GHz silicon, greatly reducing design time and enabling far wider use of asynchronous technology.—Montek Singh (UNC Chapel Hill) and Luciano Lavagno (Politecnico di Torino)

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cover image IEEE Design & Test
IEEE Design & Test  Volume 28, Issue 5
September 2011
114 pages

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 September 2011

Author Tags

  1. asynchronous design
  2. asynchronous place and route
  3. communicating sequential processes
  4. design and test
  5. high performance
  6. slack matching

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  • (2020)DaliProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415689(1-9)Online publication date: 2-Nov-2020
  • (2017)Closing the Accuracy Gap of Static Performance Analysis of Asynchronous CircuitsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062211(1-6)Online publication date: 18-Jun-2017
  • (2017)ReconditioningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.257184036:2(265-278)Online publication date: 1-Feb-2017
  • (2016)Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuitsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972051(1042-1047)Online publication date: 14-Mar-2016
  • (2016)Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applicationsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972004(850-853)Online publication date: 14-Mar-2016
  • (2016)Timing Path-Driven Cycle Cutting for Sequential ControllersACM Transactions on Design Automation of Electronic Systems10.1145/289347321:4(1-25)Online publication date: 22-Jun-2016
  • (2016)Detailed Placement Algorithm for VLSI Design With Double-Row Height Standard CellsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.251114135:9(1569-1573)Online publication date: 1-Sep-2016
  • (2015)Logical equivalence checking of asynchronous circuits using commercial toolsProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757173(1563-1566)Online publication date: 9-Mar-2015
  • (2015)The fast evolving landscape of on-chip communicationDesign Automation for Embedded Systems10.1007/s10617-014-9137-619:1-2(59-76)Online publication date: 1-Mar-2015
  • (2014)Asynchronous circuit placement by lagrangian relaxationProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691496(641-646)Online publication date: 3-Nov-2014
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