Article

Transforming SystemC Transaction Level Models into UPPAAL timed automata

Authors:

Paula Herber,

Marcel Pockrandt,

Sabine GlesnerAuthors Info & Claims

MEMOCODE '11: Proceedings of the Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign

Pages 161 - 170

https://doi.org/10.1109/MEMCOD.2011.5970523

Published: 01 July 2011 Publication History

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Abstract

The SystemC Transaction Level Modeling (TLM) standard is widely used for modeling and simulation in hardware/software co-design. However, the semantics of the TLM core interfaces is only informally defined. This makes it impossible to apply formal verification techniques to transaction level models that conform to the TLM standard. To solve this problem, we propose a formal semantics of the TLM transport mechanisms using timed automata. We achieve this by providing a set of timed automata templates that precisely capture the semantics of the TLM core interfaces. Then, we use this set to transform a given SystemC-TLM model into a semantically equivalent timed automata model. The transformation is an extension of our previously proposed transformation from SystemC into Uppaal timed automata and can be used to verify safety, liveness, and timing properties of TLM models using the Uppaal model checker. We demonstrate the applicability and performance of our approach with two case studies, namely a loosely-timed model that uses a blocking transport and an approximately-timed model that uses a 4-phase non-blocking transport.

References

[1]

IEEE Standards Association, "IEEE Std. 1666-2005, Open SystemC Language Reference Manual," 2005.

Google Scholar

[2]

Open SystemC Initiative, "TLM 2.0 Reference," 2009.

Google Scholar

[3]

P. Herber, J. Fellmuth, and S. Glesner, "Model Checking SystemC Designs Using Timed Automata," in Int. Conf. on HW/SW Codesign and System Synthesis. ACM press, 2008.

Digital Library

Google Scholar

[4]

G. Behrmann, A. David, and K. G. Larsen, "A Tutorial on UPPAAL," in Formal Methods for the Design of Real-Time Systems, ser. LNCS 3185. Springer, 2004.

Google Scholar

[5]

D. Große, U. Kühne, and R. Drechsler, "HW/SW Co-Verification of Embedded Systems using Bounded Model Checking," in Great Lakes Symposium on VLSI. ACM, 2006.

Digital Library

Google Scholar

[6]

A. Habibi, H. Moinudeen, and S. Tahar, "Generating Finite State Machines from SystemC," in Design, Automation and Test in Europe. IEEE Press, 2006.

Digital Library

Google Scholar

[7]

C. Traulsen, J. Cornet, M. Moy, and F. Maraninchi:, "A SystemC/TLM semantics in Promela and its possible applications," in Workshop on Model Checking Software, ser. LNCS 4595. Springer, 2007.

Digital Library

Google Scholar

[8]

Y. Zhang, F. Vedrine, and B. Monsuez, "SystemC Waiting-State Automata," in Int. Workshop on Verification and Evaluation of Computer and Communication Systems, 2007.

Digital Library

Google Scholar

[9]

K. L. Man, "An Overview of SystemCFL," in Research in Microelectronics and Electronics, vol. 1, 2005.

Google Scholar

[10]

D. Karlsson, P. Eles, and Z. Peng, "Formal verification of SystemC Designs using a Petri-Net based Representation," in Design, Automation and Test in Europe. IEEE Press, 2006.

Digital Library

Google Scholar

[11]

B. Niemann and C. Haubelt, "Formalizing TLM with Communicating State Machines," Forum on specification and Design Languages, 2006.

Google Scholar

[12]

D. Große, H. M. Le, and R. Drechsler, "Proving Transaction and System-level Properties of Untimed SystemC TLM Designs," in MEMOCODE, 2010.

Google Scholar

[13]

N. Bombieri, F. Fummi, and V. Guarnieri, "Model Checking on TLM-2.0 IPs through automatic TLM-to-RTL Synthesis," in VLSI System on Chip Conference. IEEE Press, 2010.

Google Scholar

[14]

R. Alur and D. L. Dill, "A Theory of Timed Automata," Theoretical Computer Science, vol. 126, 1994.

Digital Library

Google Scholar

Cited By

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Pieper PHerdt VGroße DDrechsler ROshana R(2022)Verifying SystemC TLM peripherals using modern C++ symbolic execution toolsProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530604(1177-1182)Online publication date: 10-Jul-2022
https://dl.acm.org/doi/10.1145/3489517.3530604
Hajisheykhi RRoohitavaf MEbnenasir AKulkarni S(undefined)A framework for verification of SystemC TLM programs with model slicing: A case study2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)10.1145/2897937.2897961(1-6)
https://dl.acm.org/doi/10.1145/2897937.2897961

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MEMOCODE '11: Proceedings of the Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign

July 2011

204 pages

ISBN:9781457701184

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IEEE Computer Society

United States

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Published: 01 July 2011

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Pieper PHerdt VGroße DDrechsler ROshana R(2022)Verifying SystemC TLM peripherals using modern C++ symbolic execution toolsProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530604(1177-1182)Online publication date: 10-Jul-2022
https://dl.acm.org/doi/10.1145/3489517.3530604
Hajisheykhi RRoohitavaf MEbnenasir AKulkarni S(undefined)A framework for verification of SystemC TLM programs with model slicing: A case study2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)10.1145/2897937.2897961(1-6)
https://dl.acm.org/doi/10.1145/2897937.2897961

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STATE -- A SystemC to Timed Automata Transformation Engine

SystemC transaction level models and RTL verification

Verification of Transaction-Level SystemC models using RTL Testbenches

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