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FabScalar: Automating Superscalar Core Design

Authors:

Eric RotenbergAuthors Info & Claims

IEEE Micro, Volume 32, Issue 3

Pages 48 - 59

https://doi.org/10.1109/MM.2012.23

Published: 01 May 2012 Publication History

Abstract

Providing multiple superscalar core types on a chip, each tailored to different classes of instruction-level behavior, is an exciting direction for increasing processor performance and energy efficiency. Unfortunately, processor design and verification effort increases with each additional core type, limiting the microarchitectural diversity that can be practically implemented. FabScalar aims to automate superscalar core design, opening up processor design to microarchitectural diversity and its many opportunities.

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Zhang SWright ABourgeat T(2019)Composable Building Blocks to Open Up Processor DesignIEEE Micro10.1109/MM.2019.291001239:3(47-55)Online publication date: 1-May-2019
https://dl.acm.org/doi/10.1109/MM.2019.2910012
Gebregiorgis ATahoori M(2018)Fine-Grained Energy-Constrained Microprocessor Pipeline DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.276754326:3(457-469)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.1109/TVLSI.2017.2767543
Zhang SWright ABourgeat TArvind Oskin MInoue K(2018)Composable building blocks to open up processor designProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00015(68-81)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00015
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Published In

IEEE Micro Volume 32, Issue 3

May 2012

140 pages

ISSN:0272-1732

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Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 May 2012

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Zhang SWright ABourgeat T(2019)Composable Building Blocks to Open Up Processor DesignIEEE Micro10.1109/MM.2019.291001239:3(47-55)Online publication date: 1-May-2019
https://dl.acm.org/doi/10.1109/MM.2019.2910012
Gebregiorgis ATahoori M(2018)Fine-Grained Energy-Constrained Microprocessor Pipeline DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.276754326:3(457-469)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.1109/TVLSI.2017.2767543
Zhang SWright ABourgeat TArvind Oskin MInoue K(2018)Composable building blocks to open up processor designProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00015(68-81)Online publication date: 20-Oct-2018
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Chang TYao ZJackson PRand BWentzlaff DHunter HMoreno JEmer JSanchez D(2017)Architectural tradeoffs for biodegradable computingProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123980(706-717)Online publication date: 14-Oct-2017
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Gebregiorgis AGolanbari MKiamehr SOboril FTahoori M(2016)Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline OptimizationProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934635(272-277)Online publication date: 8-Aug-2016
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Oboril FTahoori M(2015)Exploiting Instruction Set Encoding for Aging-Aware Microprocessor DesignACM Transactions on Design Automation of Electronic Systems10.1145/278343521:1(1-26)Online publication date: 2-Dec-2015
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Oboril FTahoori MMacii E(2013)MTTF-balanced pipeline designProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485356(270-275)Online publication date: 18-Mar-2013
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Luo YHsu WZhai A(2013)The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread executionACM Transactions on Architecture and Code Optimization10.1145/2541228.254123310:4(1-29)Online publication date: 1-Dec-2013
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Oboril FFirouzi FKiamehr STahoori MJerraya ACarloni LChang NFummi F(2012)Reducing NBTI-induced processor wearout by exploiting the timing slack of instructionsProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380514(443-452)Online publication date: 7-Oct-2012
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Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme

FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

Author retrospective for software trace cache

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