IEEE Micro

This column discusses the process of choosing articles from the computer architecture conferences of 2011 for the Top Picks issue. It also acknowledges the 100th column of Micro Economics and the new cover artist for IEEE Micro.

This special issue is the ninth in an important tradition in the computer architecture community: IEEE Micro's Top Picks from the Computer Architecture Conferences. This tradition provides a means for sharing a sample of the best papers published in ...

Programming GPUs is challenging for applications with irregular fine-grained communication between threads. To improve the programmability of GPUs and thus extend their usage to a wider range of applications, the authors propose to enable transactional ...

To meet rapidly growing performance demands and energy constraints, future chips will likely feature thousands of on-die resources. Existing network-on-chip solutions were not designed for scalability and will be unable to meet future interconnect ...

The Vantage cache-partitioning technique enables configurability and quality-of-service guarantees in large-scale chip multiprocessors with shared caches. Caches can have hundreds of partitions with sizes specified at cache line granularity, while ...

Unlike threads in parallel programs created by conventional programming, data-triggered threads are initiated when a memory value is changed. By expressing computation through these threads, computation is executed only when the data changes and is ...

Providing multiple superscalar core types on a chip, each tailored to different classes of instruction-level behavior, is an exciting direction for increasing processor performance and energy efficiency. Unfortunately, processor design and verification ...

Main memory accounts for a growing fraction of server energy usage. Investigating active low-power modes for managing main memory, with a system called MemScale, the authors offer a solution for performance-aware energy management. By creating a set of ...

This work efficiently enables conventional block sizes for very large die-stacked DRAM caches with two innovations: it makes hits faster with compound-access scheduling and misses faster with a MissMap. The combination of these mechanisms enables the ...

Free-p—fine-grained remapping with error checking and correcting (ECC) and embedded pointers—remaps worn-out nonvolatile RAM (NVRAM) blocks at a fine granularity without requiring large dedicated storage and protects NVRAM against both hard and soft ...

Precisely predicting performance degradation due to colocating multiple executing applications on a single machine is critical for improving utilization in modern warehouse-scale computers (WSCs). Bubble-Up is the first mechanism for such precise ...

Networking consumes up to 33 percent of modern data center power. Network switches are the key source of inefficiency: a switch traversal costs an order of magnitude more than a link traversal. The authors propose a new high-radix switch architecture ...

Systematically exploring power, performance, and energy sheds new light on the clash of two trends that unfolded over the past decade: the rise of parallel processors in response to technology constraints on power, clock speed, and wire delay; and the ...

A key question for the microprocessor research and design community is whether scaling multicores will provide the performance and value needed to scale down many more technology generations. To provide a quantitative answer to this question, a ...

This column examines the texture cache, an essential component of modern GPUs that plays an important role in achieving real-time performance when generating realistic images. GPUs have many components and the texture cache is only one of them. But it ...

Borrowing "The Secret Life of Walter Mitty" by James Thurber, this column explores what a typical day would be like for a Mitty-like programmer in the Silicon Valley of today.