research-article

BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs

Authors:

Michael Bedford TaylorAuthors Info & Claims

IEEE Micro, Volume 40, Issue 4

Pages 93 - 102

https://doi.org/10.1109/MM.2020.2996145

Published: 01 July 2020 Publication History

Abstract

This article introduces BlackParrot, which aims to be the default open-source, Linux-capable, cache-coherent, 64-bit RISC-V multicore used by the world. In executing this goal, our research aims to advance the world's knowledge about the “software engineering of hardware.” Although originally bootstrapped by the University of Washington and Boston University via DARPA funding, BlackParrot strives to be community driven and infrastructure agnostic; a multicore which is Pareto optimal in terms of power, performance, area, and complexity. In order to ensure BlackParrot is easy to use, extend, and, most importantly, trust, development is guided by three core principles: Be Tiny, Be Modular, and Be Friendly. Development efforts have prioritized the use of intentional interfaces and modularity and silicon validation as first-order design metrics, so that users can quickly get started and trust that their design will perform as expected when deployed. BlackParrot has been validated in a GlobalFoundries 12-nm FinFET tapeout. BlackParrot is ideal as a standalone Linux processor or as a malleable fabric for an agile accelerator SoC design flow.

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Liu XGonzalez-Guerrero PPeng IMinnich RGokhale M(2023)Accelerator integration in a tile-based SoC: lessons learned with a hardware floating point compression engineProceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis10.1145/3624062.3624245(1662-1669)Online publication date: 12-Nov-2023
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BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs

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Published In

IEEE Micro Volume 40, Issue 4

July-Aug. 2020

121 pages

ISSN:0272-1732

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 July 2020

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Faye JHaggui NKermarrec FMartin KBhattacharyya SNezan JPelcat M(2024)Scratchy: A Class of Adaptable Architectures with Software-Managed Communication for Edge Streaming ApplicationsDesign and Architectures for Signal and Image Processing10.1007/978-3-031-62874-0_6(68-79)Online publication date: 17-Jan-2024
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Liu XGonzalez-Guerrero PPeng IMinnich RGokhale M(2023)Accelerator integration in a tile-based SoC: lessons learned with a hardware floating point compression engineProceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis10.1145/3624062.3624245(1662-1669)Online publication date: 12-Nov-2023
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