Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/3610396.3623265acmconferencesArticle/Chapter ViewAbstractPublication PagesmicroConference Proceedingsconference-collections
research-article

OpenPiton Optimizations Towards High Performance Manycores

Published: 28 October 2023 Publication History

Abstract

In recent years, numerous multicore RISC-V platforms have emerged. Within the RISC-V ecosystem, Networks-on-Chip (NoCs) such as OpenPiton are employed in designs that aim to scale to a large number of cores. This paper presents a set of extensions and optimizations to OpenPiton for high-performance manycores. The key contributions are enabling multiple memory controllers, supporting router bypassing and NoC concentration, and adding support for configurable cache sizes and cache block sizes. On a 64-core manycore architecture, these new features and optimizations provide a geometric mean speedup of 6.5x compared to the OpenPiton baseline.

References

[1]
D.H. Bailey, E. Barszcz, J.T. Barton, D.S. Browning, R.L. Carter, L. Dagum, R.A. Fatoohi, P.O. Frederickson, T.A. Lasinski, R.S. Schreiber, H.D. Simon, V. Venkatakrishnan, and S.K. Weeratunga. 1991. The Nas Parallel Benchmarks. Int. J. High Perform. Comput. Appl. 5, 3 (sep 1991), 63--73. https://doi.org/10.1177/109434209100500306
[2]
Jonathan Balkind, Katie Lim, Michael Schaffner, Fei Gao, Grigory Chirkov, Ang Li, Alexey Lavrov, Tri M. Nguyen, Yaosheng Fu, Florian Zaruba, Kunal Gulati, Luca Benini, and David Wentzlaff. 2020. BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA Research. In Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (Lausanne, Switzerland) (ASPLOS '20). Association for Computing Machinery, New York, NY, USA, 699--714. https://doi.org/10.1145/3373376.3378479
[3]
Jonathan Balkind, Michael McKeown, Yaosheng Fu, Tri Minh Nguyen, Yanqi Zhou, Alexey Lavrov, Mohammad Shahrad, Adi Fuchs, Samuel Payne, Xiaohua Liang, Matthew Matl, and David Wentzlaff. 2016. OpenPiton: An Open Source Manycore Research Framework. In Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2016, Atlanta, GA, USA, April 2-6, 2016, Tom Conte and Yuanyuan Zhou (Eds.). ACM, 217--232. https://doi.org/10.1145/2872362.2872414
[4]
Jonathan Balkind, Michael Schaffner, Katie Lim, Florian Zaruba, Fei Gao, Jinzheng Tu, David Wentzlaff, and Luca Benini. 2019. OpenPiton+Ariane: The First SMP Linux-booting RISC-V System Scaling from One to Many Cores. In Workshop on Computer Architecture Research with RISC-V, CARRV 2019, Phoenix, AZ, USA, June 22, 2019. https://carrv.github.io/2019/papers/carrv2019_paper_12.pdf
[5]
Alex Bradbury, Gavin Robert Ferris, and Robert D. Mullins. 2014. Tagged memory and minion cores in the lowRISC SoC.
[6]
Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiél Leyva, Guillem López-Paradís, Jonnatan Mendoza, Francesco Minervini, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Víctor Soria, Alejandro Suanes, Iván Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Víctor Montabes, Adrián Cristal, Carles Hernández, Ricardo Martínez, Miquel Moretó, Francesc Moll, Oscar Palomar, Marco A. Ramírez, Antonio Rubio, Jordi Sacristán, Francesc Serra-Graells, Nehir Sonmez, Lluís Terés, Osman Unsal, Mateo Valero, and Luís Villa. 2022. DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. In 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS). 1--6. https://doi.org/10.1109/DCIS55711.2022.9970128
[7]
RISC-V International. 2012. riscv-tests. https://github.com/riscv-software-src/riscv-tests. Accessed Aug. 2023.
[8]
Ahmed Kamaleldin and Diana Göhringer. 2022. AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors. IEEE Access 10 (2022), 43895--43913. https://doi.org/10.1109/ACCESS.2022.3168686
[9]
Neiel I. Leyva-Santes, Ivan Pérez, César A. Hernández-Calderón, Enrique Vallejo, Miquel Moretó, Ramón Beivide, Marco A. Ramírez-Salinas, and Luis A. Villa-Vargas. 2019. Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip. In Supercomputing, Moisés Torres and Jaime Klapp (Eds.). Springer International Publishing, Cham, 237--248.
[10]
Katie Lim, Jonathan Balkind, and David Wentzlaff. 2018. JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores. https://doi.org/10.48550/ARXIV.1811.08091
[11]
Guillem López-Paradís, Brian Li, Adrià Armejach, Wallentowitzm Stefan, Miquel Moretó, and Jonathan Balkind. 2023. Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-MPI. In Proceedings of the Design, Automation and Test in Europe Conference (DATE'23).
[12]
Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, and Luca P. Carloni. 2020. Agile SoC Development with Open ESP. In Proceedings of the 39th International Conference on Computer-Aided Design (Virtual Event, USA) (ICCAD '20). Association for Computing Machinery, New York, NY, USA, Article 96, 9 pages. https://doi.org/10.1145/3400302.3415753
[13]
Larry McVoy and Carl Staelin. 1996. Lmbench: Portable Tools for Performance Analysis. In Proceedings of the 1996 Annual Conference on USENIX Annual Technical Conference (San Diego, CA) (ATEC 96). USENIX Association, USA, 23.
[14]
Alireza Monemi, Iván Pérez, Neiel Leyva, Enrique Vallejo, Ramón Beivide, and Miquel Moretó. 2021. PlugSMART: A Pluggable Open-Source Module to Implement Multihop Bypass in Networks-on-Chip. In Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip (Virtual Event) (NOCS '21). Association for Computing Machinery, New York, NY, USA, 41--48. https://doi.org/10.1145/3479876.3481601
[15]
Alireza Monemi, Jia Wei Tang, Maurizio Palesi, and Muhammad N. Marsono. 2017. ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform. Microprocessors and Microsystems 54 (2017), 60--74. https://doi.org/10.1016/j.micpro.2017.08.007
[16]
Daniel Petrisko, Farzam Gilani, Mark Wyse, Dai Cheol Jung, Scott Davidson, Paul Gao, Chun Zhao, Zahra Azad, Sadullah Canakci, Bandhav Veluri, Tavio Guarino, Ajay Joshi, Mark Oskin, and Michael Bedford Taylor. 2020. BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs. IEEE Micro 40, 4 (2020), 93--102. https://doi.org/10.1109/MM.2020.2996145
[17]
Antonio Pullini, Davide Rossi, Igor Loi, Giuseppe Tagliavini, and Luca Benini. 2019. Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing. IEEE Journal of Solid-State Circuits 54, 7 (2019), 1970--1981. https://doi.org/10.1109/JSSC.2019.2912307

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
NoCArc '23: Proceedings of the 16th International Workshop on Network on Chip Architectures
October 2023
61 pages
ISBN:9798400703072
DOI:10.1145/3610396
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 28 October 2023

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. Network-on-chip
  2. OpenPiton
  3. high-performance computing

Qualifiers

  • Research-article
  • Research
  • Refereed limited

Conference

MICRO '23
Sponsor:

Acceptance Rates

NoCArc '23 Paper Acceptance Rate 5 of 14 submissions, 36%;
Overall Acceptance Rate 46 of 122 submissions, 38%

Upcoming Conference

MICRO '24

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • 0
    Total Citations
  • 124
    Total Downloads
  • Downloads (Last 12 months)124
  • Downloads (Last 6 weeks)7
Reflects downloads up to 15 Oct 2024

Other Metrics

Citations

View Options

Get Access

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media