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Improving the Performance of GALS-Based NoCs in the Presence of Process Variation

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J. DuatoAuthors Info & Claims

NOCS '10: Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

Pages 35 - 42

https://doi.org/10.1109/NOCS.2010.13

Published: 03 May 2010 Publication History

Abstract

Current integration scales allow designing chip multiprocessors (CMP) where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales cause some unpredictability in manufactured devices because of process variation. In NoCs,variability may affect links and routers causing that they do not match the parameters established at design time. In this paper we first analyze the way that manufacturing deviations affect the components of a NoC by applying a comprehensive and detailed variability model to 200 instances of an 8x8 mesh NoC synthesized using 45nm technology. A second contribution of this paper is showing that GALS-based NoCs present communication bottlenecks under process variation. To overcome this performance reduction we draft a novel approach, called performance domains, intended to reduce the negative impact of variability on application execution time. This mechanism is suitable when several applications are simultaneously running in the CMP chip.

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Cited By

Tang AGao XChen LJha N(2016)Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT VariationsACM Journal on Emerging Technologies in Computing Systems10.1145/279523112:4(1-21)Online publication date: 8-Mar-2016
https://dl.acm.org/doi/10.1145/2795231
Ezz-Eldin REl-Moursy MHamed H(2015)High Throughput Asynchronous NoC Design under High Process VariationIntegration, the VLSI Journal10.1016/j.vlsi.2014.10.00649:C(1-13)Online publication date: 1-Mar-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.10.006
Strano AHernández CSilla FBertozzi D(2011)Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip DesignInternational Journal of Embedded and Real-Time Communication Systems10.4018/jertcs.20111001012:4(1-20)Online publication date: 1-Oct-2011
https://dl.acm.org/doi/10.4018/jertcs.2011100101

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cover image Guide Proceedings

NOCS '10: Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

May 2010

255 pages

ISBN:9780769540535

Publisher

IEEE Computer Society

United States

Publication History

Published: 03 May 2010

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Cited By

Tang AGao XChen LJha N(2016)Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT VariationsACM Journal on Emerging Technologies in Computing Systems10.1145/279523112:4(1-21)Online publication date: 8-Mar-2016
https://dl.acm.org/doi/10.1145/2795231
Ezz-Eldin REl-Moursy MHamed H(2015)High Throughput Asynchronous NoC Design under High Process VariationIntegration, the VLSI Journal10.1016/j.vlsi.2014.10.00649:C(1-13)Online publication date: 1-Mar-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.10.006
Strano AHernández CSilla FBertozzi D(2011)Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip DesignInternational Journal of Embedded and Real-Time Communication Systems10.4018/jertcs.20111001012:4(1-20)Online publication date: 1-Oct-2011
https://dl.acm.org/doi/10.4018/jertcs.2011100101

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