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Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes

Authors:

Aoxiang Tang,

Xun Gao,

Lung-Yen Chen,

Niraj K. JhaAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 12, Issue 4

Article No.: 42, Pages 1 - 21

https://doi.org/10.1145/2795231

Published: 08 March 2016 Publication History

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Abstract

The semiconductor industry has moved to FinFETs because of their superior ability to mitigate short-channel effects relative to CMOS. Thus, good FinFET delay and power models are urgently needed to facilitate FinFET IC design at the upcoming technology nodes. Another urgent problem that needs to be addressed with continued technology scaling is how to analyze circuit performance and power consumption under process, voltage, and temperature (PVT) variations. Such variations arise due to limitations of lithography that lead to variations in the physical dimensions of the device or due to environmental variations. In this article, we propose a delay/power modeling framework for analysis of FinFET logic circuits under PVT variations. We present models for FinFET logic gates and three FinFET SRAM cells. We use GenFin, which is a genetic algorithm based statistical circuit-level delay/power optimizer, to produce the models for functional units (FUs) employed in a processor. We compare the impact of PVT variations at the 22nm and 14nm FinFET technology nodes. We evaluate cache performance for various cache capacities and temperatures as well as that of FUs. Our device simulation results show that the 3σ/μ spread for 14nm circuits is, on average, 38.5% higher in dynamic power and 21.4% higher in logarithm of leakage power relative to 22nm FinFET circuits. However, the delay spread depends on the circuit.

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Cited By

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Li KLu JZuo HZhang G(2023)Dynamic Classifier Alignment for Unsupervised Multi-Source Domain AdaptationIEEE Transactions on Knowledge and Data Engineering10.1109/TKDE.2022.314442335:5(4727-4740)Online publication date: 1-May-2023
https://dl.acm.org/doi/10.1109/TKDE.2022.3144423
Wang JChen ZGuo JLi YLu Z(2017)ACO-Based Thermal-Aware Thread-to-Core Mapping for Dark-Silicon-Constrained CMPsIEEE Transactions on Electron Devices10.1109/TED.2017.265383864:3(930-937)Online publication date: Mar-2017
https://doi.org/10.1109/TED.2017.2653838
Girish HShashikumar D(2017)Cost-Effective Computational Modeling of Fault Tolerant Optimization of FinFET-Based SRAM CellsCybernetics and Mathematics Applications in Intelligent Systems10.1007/978-3-319-57264-2_1(1-12)Online publication date: 7-Apr-2017
https://doi.org/10.1007/978-3-319-57264-2_1

Index Terms

Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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Reviewer: Xinfei Guo

Driven by the increasing demands of low power and high performance, the semiconductor industry has pushed the device down to below 20 nanometer (nm) scale. Downscaling introduced several challenges, among which short channel effect is one of the most critical ones. The direct impact for short channel effect is that it is very hard to turn off the transistor, which means the undesired leakage current will be large. The industry introduced FinFET, a tri-gate 3D transistor that has a very good ability to mitigate short channel effect while satisfying the device-shrinking requirement for extending Moore's law. Due to the physical differences between FinFET and planar devices, the new modeling and design methodology need to be adjusted based on the uniqueness of FinFET devices, such as the effects of process, voltage, and temperature (PVT) variations that are induced during fabrication and operations. Also, other research questions include how these device- and circuit-level features affect the architecture-level design, and how these features can improve the architecture-level metrics. In this paper, Tang et al. address the above questions by proposing a delay and power modeling framework for analyzing FinFET logic circuits under PVT variations; the circuit-level model is plugged into the architecture-level simulators to evaluate the overall impact at a higher level. The flow is detailed in the paper. For example, at the device level, the TCAD tool is used for obtaining the FinFET device-level parameters that can be used in the circuit-level simulations. PVT variations are introduced as a statistical distribution. At the architecture level, both cache and functional unit (FU) are used as the evaluation platform. A performance/power modeling framework McPAT is used as the architecture-level simulator, which works together with the Synopsys design compiler and a genetic algorithm called GenFin. Overall, the modeling framework takes care of the FinFET device-level characteristics and transforms these impacts to the higher level while considering the PVT variations. As for the results, the paper compares the power and performance between the 14 nm and 22 nm nodes. The modeling framework captures the impact of PVT variations statistically (error is below 3.3 percent). The proposed modeling framework is robust and can assist the circuit designers and computer architects to optimize power and performance metrics for FinFET design. The flow can even be adapted to other technologies for doing similar analysis. The simulated results also show that 14 nm FinFET has a wide range of variability, and this indicates that the PVT variations in FinFET design need to be addressed in a very early design stage and in a systematic way so that the overall design is robust. Online Computing Reviews Service

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cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 12, Issue 4

Regular Papers

July 2016

394 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/2856147

Editor:
Yuan Xie
University of California, Santa Barbara, USA

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Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 March 2016

Accepted: 01 June 2015

Revised: 01 April 2015

Received: 01 December 2014

Published in JETC Volume 12, Issue 4

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Li KLu JZuo HZhang G(2023)Dynamic Classifier Alignment for Unsupervised Multi-Source Domain AdaptationIEEE Transactions on Knowledge and Data Engineering10.1109/TKDE.2022.314442335:5(4727-4740)Online publication date: 1-May-2023
https://dl.acm.org/doi/10.1109/TKDE.2022.3144423
Wang JChen ZGuo JLi YLu Z(2017)ACO-Based Thermal-Aware Thread-to-Core Mapping for Dark-Silicon-Constrained CMPsIEEE Transactions on Electron Devices10.1109/TED.2017.265383864:3(930-937)Online publication date: Mar-2017
https://doi.org/10.1109/TED.2017.2653838
Girish HShashikumar D(2017)Cost-Effective Computational Modeling of Fault Tolerant Optimization of FinFET-Based SRAM CellsCybernetics and Mathematics Applications in Intelligent Systems10.1007/978-3-319-57264-2_1(1-12)Online publication date: 7-Apr-2017
https://doi.org/10.1007/978-3-319-57264-2_1

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Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment

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Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment

Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology

McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations

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