Article

Full chip leakage estimation considering power supply and temperature variations

Authors:

Haihua Su,

Frank Liu,

Anirudh Devgan,

Emrah Acar, and

Sani NassifAuthors Info & Claims

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

August 2003

Pages 78 - 83

https://doi.org/10.1145/871506.871529

Published: 25 August 2003 Publication History

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Abstract

Leakage power is emerging as a key design challenge in current and future CMOS designs. Since leakage is critically dependent on operating temperature and power supply, we present a full chip leakage estimation technique which accurately accounts for power supply and temperature variations. State of the art techniques are used to compute the thermal and power supply profile of the entire chip. Closed-form models are presented which relate leakage to temperature and VDD variations. These models coupled with the thermal and VDD profile are used to generate an accurate full chip leakage estimation technique considering environmental variations. The results of this approach are demonstrated on large-scale industrial designs.

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Patil C(2021)A Novel Thermal Modeling of Through Silicon Vias in 3-D IC structuresInternational Journal of Materials10.46300/91018.2020.7.197(104-110)Online publication date: 15-Jan-2021
https://doi.org/10.46300/91018.2020.7.19
Faezi SYasaei RBarua AFaruque M(2021)Brain-Inspired Golden Chip Free Hardware Trojan DetectionIEEE Transactions on Information Forensics and Security10.1109/TIFS.2021.306298916(2697-2708)Online publication date: 2021
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Narayan AThonnart YVivet PCoskun A(2021)PROWAVES: Proactive Runtime Wavelength Selection for Energy-Efficient Photonic NoCsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.303732740:10(2156-2169)Online publication date: Oct-2021
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Index Terms

Full chip leakage estimation considering power supply and temperature variations
1. Computing methodologies
  1. Modeling and simulation

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Published In

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

August 2003

502 pages

ISBN:158113682X

DOI:10.1145/871506

General Chairs:
Ingrid Verbauwhede
University of California, Los Angeles, CA
,
Hyung Roh
Samsung Electronics

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 25 August 2003

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ISLPED03: International Symposium on Low Power Electronics and Design

August 25 - 27, 2003

Seoul, Korea

Acceptance Rates

ISLPED '03 Paper Acceptance Rate 90 of 221 submissions, 41%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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ISLPED '24

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sigda

ACM/IEEE International Symposium on Low Power Electronics and Design

August 5 - 7, 2024

Newport Beach , CA , USA

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Patil C(2021)A Novel Thermal Modeling of Through Silicon Vias in 3-D IC structuresInternational Journal of Materials10.46300/91018.2020.7.197(104-110)Online publication date: 15-Jan-2021
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Faezi SYasaei RBarua AFaruque M(2021)Brain-Inspired Golden Chip Free Hardware Trojan DetectionIEEE Transactions on Information Forensics and Security10.1109/TIFS.2021.306298916(2697-2708)Online publication date: 2021
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Narayan AThonnart YVivet PCoskun A(2021)PROWAVES: Proactive Runtime Wavelength Selection for Energy-Efficient Photonic NoCsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.303732740:10(2156-2169)Online publication date: Oct-2021
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Jalili MManousakis IGoiri ÍMisra PRaniwala AAlissa HRamakrishnan BTuma PBelady CFontoura MBianchini RMartínez JDuato JJohn L(2021)Cost-efficient overclocking in immersion-cooled datacentersProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00055(623-636)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00055
Li LGuo SMeng LZhai HHui ZMa BShen S(2020)An Improved Q-Learning for System Power Optimization with Temperature, Performance and Energy Constraint Modeling2020 IEEE Conference on Telecommunications, Optics and Computer Science (TOCS)10.1109/TOCS50858.2020.9339699(348-354)Online publication date: 11-Dec-2020
https://doi.org/10.1109/TOCS50858.2020.9339699
Sarkinen JBrannvall RGustafsson JSummers J(2020) Experimental Analysis of Server Fan Control Strategies for Improved Data Center Air-based Thermal Management * 2020 19th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)10.1109/ITherm45881.2020.9190337(341-349)Online publication date: Jul-2020
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Zhang CMihajlovic MPavlidis V(2019)Adaptive Transient Leakage-Aware Linearised Model for Thermal Analysis of 3-D ICs2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8714867(268-271)Online publication date: Mar-2019
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Sultan HChauhan ASarangi S(2019)A Survey of Chip-level Thermal SimulatorsACM Computing Surveys10.1145/330954452:2(1-35)Online publication date: 30-Apr-2019
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Asad ADorostkar AMohammadi F(2018)A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon ageEURASIP Journal on Embedded Systems10.1186/s13639-018-0086-12018:1Online publication date: 27-Jul-2018
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Helms DEilers RMetzdorf MNebel W(2018)Leakage Models for High-Level Power EstimationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.276051937:8(1627-1639)Online publication date: Aug-2018
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Modeling and estimation of full-chip leakage current considering within-die correlation

A novel adaptive design methodology for minimum leakage power considering PVT variations on nanoscale VLSI systems

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Modeling and estimation of full-chip leakage current considering within-die correlation

A novel adaptive design methodology for minimum leakage power considering PVT variations on nanoscale VLSI systems

Nanoscale CMOS circuit leakage power reduction by double-gate device

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