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Statistical estimation of leakage current considering inter- and intra-die process variation

Published: 25 August 2003 Publication History
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  • Abstract

    We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte-Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.

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      cover image ACM Conferences
      ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design
      August 2003
      502 pages
      ISBN:158113682X
      DOI:10.1145/871506
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      Publication History

      Published: 25 August 2003

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      Author Tags

      1. Monte Carlo
      2. leakage current
      3. variability

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      ISLPED '03 Paper Acceptance Rate 90 of 221 submissions, 41%;
      Overall Acceptance Rate 398 of 1,159 submissions, 34%

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      • (2021)Estimating Operational Age of an Integrated CircuitJournal of Electronic Testing10.1007/s10836-021-05927-3Online publication date: 7-Jun-2021
      • (2020)Additive Statistical Leakage Analysis Using Exponential Mixture ModelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.2975154(1-1)Online publication date: 2020
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      • (2019)Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)10.1109/HST.2019.8741032(72-80)Online publication date: May-2019
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      • (2018)An Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Current DistributionIEEE Journal of the Electron Devices Society10.1109/JEDS.2017.27580266(494-499)Online publication date: 2018
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      • (2016)Hierarchical Statistical Leakage Analysis and Its ApplicationACM Transactions on Design Automation of Electronic Systems10.1145/289682021:4(1-22)Online publication date: 2-Sep-2016
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