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Hierarchical Statistical Leakage Analysis and Its Application

Published: 02 September 2016 Publication History

Abstract

In this article, we investigate a hierarchical statistical leakage analysis (HSLA) design flow where module-level statistical leakage models supplied by IP vendors are used to improve the efficiency and capacity of SoC statistical leakage power analysis. To solve the challenges of incorporating spatial correlations between IP modules at system level, we first propose a method to extract correlation-inclusive leakage models. Then a method to handle the spatial correlations at system level is proposed. Using this method, the runtime of system statistical leakage analysis (SLA) can be significantly improved without disclosing the netlists of the IP modules. Experimental results demonstrate that the proposed HSLA method is about 100 times faster than gate-level full-chip SLA methods while maintaining the accuracy. In addition, we also investigate one application of this HSLA method, a leakage-yield-driven floorplanning framework, to demonstrate the benefits of such an HSLA method in practice. Moreover, an optimized hierarchical leakage analysis method dedicated to the floorplanning framework is proposed. The effectiveness of the floorplanning framework and the optimized method are confirmed by extensive experimental results.

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  • (2024)Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power OptimizationProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685949(1-7)Online publication date: 9-Sep-2024
  • (2023)FastPassProceedings of the 2023 International Symposium on Physical Design10.1145/3569052.3571879(9-16)Online publication date: 26-Mar-2023
  • (2023)FastPass: A Fast Pin Access Analysis Framework for Detailed Routability EnhancementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334630243:5(1566-1579)Online publication date: 25-Dec-2023
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      Published In

      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 21, Issue 4
      September 2016
      423 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/2939671
      • Editor:
      • Naehyuck Chang
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 02 September 2016
      Accepted: 01 February 2016
      Revised: 01 January 2016
      Received: 01 October 2015
      Published in TODAES Volume 21, Issue 4

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      Author Tags

      1. Process variations
      2. hierarchical analysis
      3. leakage model extraction
      4. statistical leakage analysis
      5. variation-aware floorplanning

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      • Project PowerEval (funded by Bayerisches Wirtschafsministerium)

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      View all
      • (2024)Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power OptimizationProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685949(1-7)Online publication date: 9-Sep-2024
      • (2023)FastPassProceedings of the 2023 International Symposium on Physical Design10.1145/3569052.3571879(9-16)Online publication date: 26-Mar-2023
      • (2023)FastPass: A Fast Pin Access Analysis Framework for Detailed Routability EnhancementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334630243:5(1566-1579)Online publication date: 25-Dec-2023
      • (2019)HydraRouteProceedings of the 2019 on Great Lakes Symposium on VLSI10.1145/3299874.3317997(177-182)Online publication date: 13-May-2019

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