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Statistical estimation of leakage current considering inter- and intra-die process variation

Published: 25 August 2003 Publication History

Abstract

We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte-Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.

References

[1]
C. Hu, "Device and technology impact on low power electronics," Low Power Design Methodologies, ed. Jan Rabaey, Kluwer, pp. 21-35, 1996.
[2]
<http://developer.intel.com/design/mobile/datashts>
[3]
S. Sirichotiyakul, T. Edwards, C. Oh, J. Zuo, A. Dharchoudhury, R. Panda, and D. Blaauw, "Standby power minimization through simultaneous threshold voltage and circuit sizing," Proc. DAC, pp. 436--441, 1999.
[4]
Y. Ye, S. Borkar, and V. De, "A new technique for standby leakage reduction in high-performance circuits," Proc. Symposium on VLSI Circuits, pp. 40--41, 1998.
[5]
J. Halter and F. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," Proc. CICC, pp. 475--478, 1997.
[6]
S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V power supply high-speed digital circuit technology with multithreshold voltage CMOS," IEEE Journal of Solid-State Circuits, vol. 30, pp. 847--854, Aug. 1995.
[7]
R.K. Krishnamurthy, A. Alvandpour, V. De, and S. Borkar, "High-performance and low-power challenges for sub-70nm microprocessor circuits," Proc. CICC, pp. 125--128, 2002.
[8]
P. Pant, V. De, and A. Chatterjee, "Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks," Proc. DAC, pp. 403--408, 1997.
[9]
International Technology Roadmap for Semiconductors, 2001.
[10]
S. Narendra, V. De, S. Borkar, and A. Chandrakasan, "Full chip sub-threshold leakage power prediction model for sub-0.18um CMOS," Proc. ISLPED, pp.19--23, 2002.
[11]
S. Tyagi et al, "A 130nm generation logic technology featuring 70nm transistors, dual Vt transistors and 6 layers of Cu interconnect," Proc. IEDM, pp. 567--570, 2000.
[12]
J. Kao, S. Narendra, and A. Chandrakasan, "Subthreshold leakage modeling and reduction techniques," Proc. ICCAD, pp. 141--148, Nov. 2002.
[13]
A. Srivastava, R. Bai, D. Blaauw, and D. Sylvester, "Modeling and analysis of leakage power considering within-die process variations," Proc. ISLPED, pp. 64--67, 2002.
[14]
A. Papoulis, Probability, Random Variables, and Stochastic Processes, McGraw-Hill Inc, New York, 1991.
[15]
A. Chandrakasan, W.J. Bowhill, and F. Fox, Design of high-performance microprocessor circuits, IEEE Press, 2001.
[16]
K.K. Ng, S.A. Eshraghi, and T.D. Stanik, "An improved generalized guide for MOSFET scaling," IEEE TED, vol.40, pp. 1893--1895, 1993.
[17]
Z. Chen, M. Johnson, L. Wei, and K. Roy, "Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks," Proc. ISLPED, pp. 239--244, 1998.
[18]
N.C. Beaulieu, A.A. Abu-Dayya, and, P.J.McLane. "Comparison of methods of computing lognormal sum distributions and outages for digital wireless applications," IEEE International Conference on Communications, vol.3 pp.1270--1275,1994.
[19]
S.C. Schwartz and Y.S. Yeh, "On the distribution function and moments of power sums with lognormal components," Bell Systems Technical Journal, vol.61, pp.1441--1462, Sept. 1982.
[20]
N. Marlow, "A normal limit theorem for power sums of independent random variables," Bell Systems Technical Journal, vol.46, pp.2081--2090, Nov. 1967.
[21]
F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran," Proc. International Symposium on Circuits and Systems, pp. 695--698, May 1989.

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    cover image ACM Conferences
    ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design
    August 2003
    502 pages
    ISBN:158113682X
    DOI:10.1145/871506
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    Publication History

    Published: 25 August 2003

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    Author Tags

    1. Monte Carlo
    2. leakage current
    3. variability

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    ISLPED '03 Paper Acceptance Rate 90 of 221 submissions, 41%;
    Overall Acceptance Rate 398 of 1,159 submissions, 34%

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    • (2022)Harnessing Voltage margins for Balanced Energy and PerformanceComputing at the EDGE10.1007/978-3-030-74536-3_3(51-90)Online publication date: 20-Sep-2022
    • (2021)Estimating Operational Age of an Integrated CircuitJournal of Electronic Testing10.1007/s10836-021-05927-3Online publication date: 7-Jun-2021
    • (2020)Additive Statistical Leakage Analysis Using Exponential Mixture ModelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.2975154(1-1)Online publication date: 2020
    • (2019)Two-Pattern ∆IDDQ Test for Recycled IC Detection2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2019.00033(82-87)Online publication date: Jan-2019
    • (2019)Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)10.1109/HST.2019.8741032(72-80)Online publication date: May-2019
    • (2018)Leakage Models for High-Level Power EstimationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.276051937:8(1627-1639)Online publication date: Aug-2018
    • (2018)An Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Current DistributionIEEE Journal of the Electron Devices Society10.1109/JEDS.2017.27580266(494-499)Online publication date: 2018
    • (2017)A novel method to characterize DRAM process variation by the analyzing stochastic properties of retention time distribution2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM)10.1109/EDTM.2017.7947550(132-133)Online publication date: Feb-2017
    • (2017)Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristics2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2017.7858343(324-329)Online publication date: Jan-2017
    • (2016)Hierarchical Statistical Leakage Analysis and Its ApplicationACM Transactions on Design Automation of Electronic Systems10.1145/289682021:4(1-22)Online publication date: 2-Sep-2016
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