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Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes

Authors:

Aoxiang Tang,

Xun Gao,

Lung-Yen Chen,

Niraj K. JhaAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 12, Issue 4

Article No.: 42, Pages 1 - 21

https://doi.org/10.1145/2795231

Published: 08 March 2016 Publication History

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Abstract

The semiconductor industry has moved to FinFETs because of their superior ability to mitigate short-channel effects relative to CMOS. Thus, good FinFET delay and power models are urgently needed to facilitate FinFET IC design at the upcoming technology nodes. Another urgent problem that needs to be addressed with continued technology scaling is how to analyze circuit performance and power consumption under process, voltage, and temperature (PVT) variations. Such variations arise due to limitations of lithography that lead to variations in the physical dimensions of the device or due to environmental variations. In this article, we propose a delay/power modeling framework for analysis of FinFET logic circuits under PVT variations. We present models for FinFET logic gates and three FinFET SRAM cells. We use GenFin, which is a genetic algorithm based statistical circuit-level delay/power optimizer, to produce the models for functional units (FUs) employed in a processor. We compare the impact of PVT variations at the 22nm and 14nm FinFET technology nodes. We evaluate cache performance for various cache capacities and temperatures as well as that of FUs. Our device simulation results show that the 3σ/μ spread for 14nm circuits is, on average, 38.5% higher in dynamic power and 21.4% higher in logarithm of leakage power relative to 22nm FinFET circuits. However, the delay spread depends on the circuit.

References

[1]

Saurabh Adya, Andrew Caldwell, Andrew B. Kahng, Igor Markov, and Jarrod Roy. 2005. Capo: A Large-Scale Fixed-Die FloorPlacer. Retrieved November 25, 2015, from http://vlsicad.eecs.umich.edu/BK/PDtools/Capo.

Google Scholar

[2]

A. Agarwal, D. Blaauw, and V. Zolotov. 2003. Statistical timing analysis for intra-die process variations with spatial correlations. In Proceedings of the International Conference on Computer-Aided Design 900--907.

Digital Library

Google Scholar

[3]

M. Alioto and G. Palumbo. 2006. Impact of supply voltage variations on full adder delay: Analysis and comparison. IEEE Transaction on Very Large Scale Integration (VLSI) Systems 14, 12, 1322--1335.

Digital Library

Google Scholar

[4]

Ajay N. Bhoj and Niraj K. Jha. 2010. Gated-diode FinFET DRAMs: Device and circuit design considerations. ACM Journal on Emerging Technologies in Computing Systems 6, 4, Article No. 12.

Digital Library

Google Scholar

[5]

A. N. Bhoj and N. K. Jha. 2013. Design of logic gates and flip-flops in high-performance FinFET technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, 11, 1975--1988.

Digital Library

Google Scholar

[6]

A. N. Bhoj, R. V. Joshi, and N. K. Jha. 2013. 3-D-TCAD-based parasitic capacitance extraction for emerging multigate devices and circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, 11, 2094--2105.

Digital Library

Google Scholar

[7]

M. M. Budnik and K. Roy. 2006. A power delivery and decoupling network minimizing ohmic loss and supply voltage variation in silicon nanoscale technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, 12, 1336--1346.

Digital Library

Google Scholar

[8]

A. Carlson, Z. Guo, S. Balasubramanian, L. T. Pang, T. J. K. Liu, and B. Nikolic. 2006. FinFET SRAM with enhanced read/write margins. In Proceedings of the 2006 IEEE International SOI Conference. 105--106.

Google Scholar

[9]

H. Chang and S. S. Sapatnekar. 2003. Statistical timing analysis considering spatial correlations using a single PERT-like traversal. In Proceedings of the International Conference on Computer-Aided Design. 621--625.

Digital Library

Google Scholar

[10]

H. Chang and S. S. Sapatnekar. 2005a. Full-chip analysis of leakage power under process variations, including spatial correlations. In Proceedings of the Design Automation Conference. 523--528.

Digital Library

Google Scholar

[11]

H. Chang and S. S. Sapatnekar. 2005b. Statistical timing analysis under spatial correlations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, 9, 1467--1482.

Digital Library

Google Scholar

[12]

Sourindra M. Chaudhuri and Niraj K. Jha. 2014. 3D vs. 2D device simulation of FinFET logic gates under PVT variations. ACM Journal on Emerging Technologies in Computing Systems 10, 3, Article No. 26.

Digital Library

Google Scholar

[13]

T.-C. Chen. 2006. Overcoming research challenges for CMOS scaling: Industry directions. In Proceedings of the International Conference on Solid-State and Integrated Circuit Technology. 4--7.

Crossref

Google Scholar

[14]

Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, and Kaushik Roy. 2006. Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. In Proceedings of the International Conference on Computer-Aided Design. 583--586.

Digital Library

Google Scholar

[15]

A. K. Coskun, T. S. Rosing, K. A Whisnant, and K. C. Gross. 2008. Static and dynamic temperature-aware scheduling for multiprocessor SoCs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, 9, 1127--1140.

Digital Library

Google Scholar

[16]

R. P. Dick and N. K. Jha. 1998. MOGAC: A multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, 10, 920--935.

Digital Library

Google Scholar

[17]

Z. Hassan, N. Allec, L. Shang, R. P. Dick, V. Venkatraman, and R. Yang. 2009. Multiscale thermal analysis for nanometer-scale integrated circuits. IEEE Transactions on Computer-Aided Design 28, 6, 860--873.

Digital Library

Google Scholar

[18]

C. Hernandez, A Roca, F. Silla, J. Flich, and J. Duato. 2010. Improving the performance of GALS-based NoCs in the presence of process variation. In Proceedings of the International Symposium on Networks-on-Chip. 35--42.

Digital Library

Google Scholar

[19]

Mark A. Horowitz. 1983. Timing Models for MOS Circuits. Technical Report. Stanford, CA.

Digital Library

Google Scholar

[20]

Pei-Yu Huang and Yu-Min Lee. 2009. Full-chip thermal analysis for the early design stage via generalized integral transforms. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, 5, 613--626.

Digital Library

Google Scholar

[21]

X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, Leland Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu. 2001. Sub-50 nm P-channel FinFET. IEEE Transactions on Electron Devices 48, 5, 880--886.

Crossref

Google Scholar

[22]

ITRS. 2012. International Technology Roadmap for Semiconductors. Retrieved November 25, 2015, from http://public.itrs.net.

Google Scholar

[23]

R. Joshi, K. Kim, and R. Kanj. 2010. FinFET SRAM design. In Proceedings of the International Conference on VLSI Design. 440--445.

Digital Library

Google Scholar

[24]

Jongyoon Jung and Taewhan Kim. 2012. Variation-aware false path analysis based on statistical dynamic timing analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, 11, 1684--1697.

Digital Library

Google Scholar

[25]

J. Kao, S. Narendra, and A. Chandrakasan. 2002. Subthreshold leakage modeling and reduction techniques {IC CAD tools}. In Proceedings of the International Conference on Computer-Aided Design. 141--148.

Digital Library

Google Scholar

[26]

Chun-Yi Lee and N. K. Jha. 2014. FinCANON: A PVT-aware integrated delay and power modeling framework for FinFET-based caches and on-chip networks. IEEE Transactions on Very Large Scale Integrated (VLSI) Systems 22, 5, 1150--1163.

Crossref

Google Scholar

[27]

B. Li, L.-S. Peh, and P. Patra. 2008. Impact of process and temperature variations on network-on-chip design exploration. In Proceedings of the International Symposium on Networks-on-Chip. 117--126.

Digital Library

Google Scholar

[28]

S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi. 2010. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proceedings of the International Symposium on Microarchitecture. 469--480.

Digital Library

Google Scholar

[29]

C.-H. Lin, J. Chang, M. Guillorn, A. Bryant, P. Oldiges, and W. Haensch. 2010. Non-planar device architecture for 15nm node: FinFET or trigate? In Proceedings of the 2010 IEEE International SOI Conference. 1--2.

Crossref

Google Scholar

[30]

C.-H. Lin, W. Haensch, P. Oldiges, H. Wang, R. Williams, J. Chang, M. Guillorn, A. Bryant, T. Yamashita, T. Standaert, H. Bu, E. Leobandung, and M. Khare. 2011. Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond. In Proceedings of the International Symposium on VLSI Technology. 16--17.

Google Scholar

[31]

P. Liu, Z. Qi, H. Li, L. Jin, W. Wu, S. X. Tan, and J. Yang. 2005. Fast thermal simulation for architecture level dynamic thermal management. In Proceedings of the International Conference on Computer-Aided Design. 639--644.

Digital Library

Google Scholar

[32]

P. Mishra, A. N. Bhoj, and N. K. Jha. 2010. Die-level leakage power analysis of FinFET circuits considering process variations. In Proceedings of the International Symposium on Quality of Electronic Design. 347--355.

Google Scholar

[33]

M. Mondal, T. Ragheb, X. Wu, A. Aziz, and Y. Massoud. 2007. Provisioning on-chip networks under buffered RC interconnect delay variations. In Proceedings of the International Symposium on Quality of Electronic Design. 873--878.

Digital Library

Google Scholar

[34]

S. Mukhopadhyay and K. Roy. 2003. Modeling and estimation of total leakage current in nano-scaled-CMOS devices considering the effect of parameter variation. In Proceedings of the International Symposium on Low Power Electronics and Design. 172--175.

Digital Library

Google Scholar

[35]

A. Muttreja, N. Agarwal, and N. K. Jha. 2007. CMOS logic design with independent-gate FinFETs. In Proceedings of the International Conference on Computer Design. 560--567.

Crossref

Google Scholar

[36]

C. Nicopoulos, S. Srinivasan, A Yanamandra, D. Park, V. Narayanan, C. R. Das, and M. J. Irwin. 2010. On the effects of process variation in network-on-chip architectures. IEEE Transactions on Dependable and Secure Computing 7, 3, 240--254.

Digital Library

Google Scholar

[37]

P. Oldiges, R. Muralidhar, P. Kulkarni, C. Lin, K. Xiu, D. Guo, M. Bajaj, and N. Sathaye. 2011. Critical analysis of 14nm device options. In Proceedings of the 2011 International Conferenceon Simulation of Semiconductor Processes and Devices. 5--8.

Crossref

Google Scholar

[38]

B. C. Schafer and T. Kim. 2008. Hotspots elimination and temperature flattening in VLSI circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, 11, 1475--1487.

Digital Library

Google Scholar

[39]

D. Sinha and H. Zhou. 2006. Statistical timing analysis with coupling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, 12, 2965--2975.

Digital Library

Google Scholar

[40]

D. Sinha, H. Zhou, and N. V. Shenoy. 2007. Advances in computation of the maximum of a set of Gaussian random variables. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, 8, 1522--1533.

Digital Library

Google Scholar

[41]

H. Su, F. Liu, A. Devgan, E. Acar, and S. Nassif. 2003. Full chip leakage-estimation considering power supply and temperature variations. In Proceedings of the International Symposium on Low Power Electronics and Design. 78--83.

Digital Library

Google Scholar

[42]

Brian Swahn and Soha Hassoun. 2006. Gate sizing: FinFETs vs 32nm bulk MOSFETs. In Proceedings of the Design Automation Conference. 528--531.

Digital Library

Google Scholar

[43]

Synopsys. 2012. Sentaurus TCAD Manuals. (2012). Available for download at http://www.synopsys.com.

Google Scholar

[44]

A. Tang and N. K. Jha. 2015. GenFin: Genetic algorithm-based multiobjective statistical FinFET logic circuit optimization using incremental statistical analysis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems PP, 99, 1.

Google Scholar

[45]

A. Tang, Y. Yang, C.-Y. Lee, and N. K. Jha. 2014. McPAT-PVT: Delay and power modeling framework for FinFET processor architectures under PVT variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, 9, 1616--1627.

Crossref

Google Scholar

[46]

Shyamkumar Thoziyoor, Naveen Muralimanohar, Jung Ho Ahn, and Norman P. Jouppi. 2008. Cacti5.1 Technical Report. Technical Report. HP Laboratories, Palo Alto, CA.

Google Scholar

[47]

C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan, D. K. Beece, J. Piaget, N. Venkateswaran, and J. G. Hemmett. 2006. First-order incremental block-based statistical timing analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, 10, 2170--2180.

Digital Library

Google Scholar

[48]

Y. Yang, Z. Gu, C. Zhu, R. P. Dick, and L. Shang. 2007. ISAC: Integrated space-and-time-adaptive chip-package thermal analysis. IEEE Transactions on Computer-Aided Design 26, 1, 86--99.

Digital Library

Google Scholar

[49]

Y. Yang and N. K. Jha. 2014. FinPrin: FinFET logic circuit analysis and optimization under PVT variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, 12, 2462--2475.

Crossref

Google Scholar

[50]

C. Zhuo, K. Chopra, D. Sylvester, and D. Blaauw. 2011. Process variation and temperature-aware full chip oxide breakdown reliability analysis. IEEE Transactions on Computer-Aided Design 30, 9, 1321--1334.

Digital Library

Google Scholar

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Index Terms

Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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Reviews

Reviewer: Xinfei Guo

Driven by the increasing demands of low power and high performance, the semiconductor industry has pushed the device down to below 20 nanometer (nm) scale. Downscaling introduced several challenges, among which short channel effect is one of the most critical ones. The direct impact for short channel effect is that it is very hard to turn off the transistor, which means the undesired leakage current will be large. The industry introduced FinFET, a tri-gate 3D transistor that has a very good ability to mitigate short channel effect while satisfying the device-shrinking requirement for extending Moore's law. Due to the physical differences between FinFET and planar devices, the new modeling and design methodology need to be adjusted based on the uniqueness of FinFET devices, such as the effects of process, voltage, and temperature (PVT) variations that are induced during fabrication and operations. Also, other research questions include how these device- and circuit-level features affect the architecture-level design, and how these features can improve the architecture-level metrics. In this paper, Tang et al. address the above questions by proposing a delay and power modeling framework for analyzing FinFET logic circuits under PVT variations; the circuit-level model is plugged into the architecture-level simulators to evaluate the overall impact at a higher level. The flow is detailed in the paper. For example, at the device level, the TCAD tool is used for obtaining the FinFET device-level parameters that can be used in the circuit-level simulations. PVT variations are introduced as a statistical distribution. At the architecture level, both cache and functional unit (FU) are used as the evaluation platform. A performance/power modeling framework McPAT is used as the architecture-level simulator, which works together with the Synopsys design compiler and a genetic algorithm called GenFin. Overall, the modeling framework takes care of the FinFET device-level characteristics and transforms these impacts to the higher level while considering the PVT variations. As for the results, the paper compares the power and performance between the 14 nm and 22 nm nodes. The modeling framework captures the impact of PVT variations statistically (error is below 3.3 percent). The proposed modeling framework is robust and can assist the circuit designers and computer architects to optimize power and performance metrics for FinFET design. The flow can even be adapted to other technologies for doing similar analysis. The simulated results also show that 14 nm FinFET has a wide range of variability, and this indicates that the PVT variations in FinFET design need to be addressed in a very early design stage and in a systematic way so that the overall design is robust. Online Computing Reviews Service

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cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 12, Issue 4

Regular Papers

July 2016

394 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/2856147

Editor:
Yuan Xie
University of California, Santa Barbara, USA

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Publication History

Published: 08 March 2016

Accepted: 01 June 2015

Revised: 01 April 2015

Received: 01 December 2014

Published in JETC Volume 12, Issue 4

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