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Fully Exploiting PCM Write Capacity Within Near Zero Cost Through Segment-Based Page Allocation
Improving the endurance of phase change memory (PCM) is a fundamental issue when PCM technology is considered as an alternative to main memory usage. Existing wear-leveling techniques overcome this challenge through constantly remapping hot virtual ...
Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories
- Christophe Layer,
- Laurent Becker,
- Kotb Jabeur,
- Sylvain Claireux,
- Bernard Dieny,
- Guillaume Prenat,
- Gregory Di Pendina,
- Stephane Gros,
- Pierre Paoli,
- Virgile Javerliac,
- Fabrice Bernard-Granger,
- Loic Decloedt
The most widely used embedded memory technology, static random access memory (SRAM), is heading toward scaling problems in advanced technology nodes due to the leakage currents caused by the quantum tunneling effect. As an alternative, spin-transfer ...
Rethinking Computer Architectures and Software Systems for Phase-Change Memory
With dramatic growth of data and rapid enhancement of computing powers, data accesses become the bottleneck restricting overall performance of a computer system. Emerging phase-change memory (PCM) is byte-addressable like DRAM, persistent like hard ...
Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability
In this article, we introduce a novel method of synthesizing symmetric Boolean functions with reversible logic gates. In contrast to earlier approaches, the proposed technique deploys a simple, regular, and cascaded structure consisting of an array of ...
Neuromorphic Processors with Memristive Synapses: Synaptic Interface and Architectural Exploration
Due to their nonvolatile nature, excellent scalability, and high density, memristive nanodevices provide a promising solution for low-cost on-chip storage. Integrating memristor-based synaptic crossbars into digital neuromorphic processors (DNPs) may ...
Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET
In this article, the RF and analog performance of junctionless accumulation-mode bulk FinFETs is analyzed by employing the variation of fin width so that it can be used as a high-efficiency RF integrated circuit design. The RF/analog performance ...
Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints
Power dissipation has become a pressing issue of concern in the designs of most electronic system as fabrication processes enter even deeper submicron regions. More specifically, leakage power plays a dominant role in system power dissipation. An ...
Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells
- Moon Seok Kim,
- William Cane-Wissing,
- Xueqing Li,
- Jack Sampson,
- Suman Datta,
- Sumeet Kumar Gupta,
- Vijaykrishnan Narayanan
Vertical tunnel field-effect transistors (VTFETs) have been extensively explored to overcome the scaling limits and to improve on-current (ION) compared to standard lateral device structures for the future technologies. The benefits in terms of reduced ...
Designing a Million-Qubit Quantum Computer Using a Resource Performance Simulator
The optimal design of a fault-tolerant quantum computer involves finding an appropriate balance between the burden of large-scale integration of noisy components and the load of improving the reliability of hardware technology. This balance can be ...
Quantum-Logic Synthesis of Hermitian Gates
In this article, the problem of synthesizing a general Hermitian quantum gate into a set of primary quantum gates is addressed. To this end, an extended version of the Jacobi approach for calculating the eigenvalues of Hermitian matrices in linear ...
Embedding of Large Boolean Functions for Reversible Logic
Reversible logic represents the basis for many emerging technologies and has recently been intensively studied. However, most of the Boolean functions of practical interest are irreversible and must be embedded into a reversible function before they can ...
Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes
The semiconductor industry has moved to FinFETs because of their superior ability to mitigate short-channel effects relative to CMOS. Thus, good FinFET delay and power models are urgently needed to facilitate FinFET IC design at the upcoming technology ...
Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs
Recently, multigate field-effect transistors have started replacing traditional planar MOSFETs to keep pace with Moore’s Law in deep submicron technology. Among different multigate transistors, FinFETs have become the preferred choice of the ...
PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer
Optical Networks-on-Chip (ONoCs) are a promising technology to overcome the bottleneck of low bandwidth of electronic Networks-on-Chip. Recent research discusses power and performance benefits of ONoCs based on their system-level design, while layout ...
A Novel Approach to Optimize Fault-Tolerant Hybrid Wireless Network-on-Chip Architectures
Wireless Network-on-Chip (WNoC) architectures have emerged as a promising interconnection infrastructure to address the performance limitations of traditional wire-based multihop NOCs. Nevertheless, the WNoC systems encounter high failure rates due to ...
A Survey of Architectural Techniques for Near-Threshold Computing
Energy efficiency has now become the primary obstacle in scaling the performance of all classes of computing systems. Low-voltage computing, specifically, near-threshold voltage computing (NTC), which involves operating the transistor very close to and ...
