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Neuromorphic Processors with Memristive Synapses: Synaptic Interface and Architectural Exploration

Published: 12 May 2016 Publication History

Abstract

Due to their nonvolatile nature, excellent scalability, and high density, memristive nanodevices provide a promising solution for low-cost on-chip storage. Integrating memristor-based synaptic crossbars into digital neuromorphic processors (DNPs) may facilitate efficient realization of brain-inspired computing. This article investigates architectural design exploration of DNPs with memristive synapses by proposing two synapse readout schemes. The key design tradeoffs involving different analog-to-digital conversions and memory accessing styles are thoroughly investigated. A novel storage strategy optimized for feedforward neural networks is proposed in this work, which greatly reduces the energy and area cost of the memristor array and its peripherals.

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  1. Neuromorphic Processors with Memristive Synapses: Synaptic Interface and Architectural Exploration

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      Published In

      cover image ACM Journal on Emerging Technologies in Computing Systems
      ACM Journal on Emerging Technologies in Computing Systems  Volume 12, Issue 4
      Regular Papers
      July 2016
      394 pages
      ISSN:1550-4832
      EISSN:1550-4840
      DOI:10.1145/2856147
      • Editor:
      • Yuan Xie
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 12 May 2016
      Accepted: 01 February 2016
      Revised: 01 January 2016
      Received: 01 September 2015
      Published in JETC Volume 12, Issue 4

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      Author Tags

      1. Neural networks
      2. analog-digital conversion
      3. digital integrated circuits
      4. memristors
      5. reconfigurable architectures

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      • (2023)Reliable Brain-inspired AI Accelerators using Classical and Emerging Memories2023 IEEE 41st VLSI Test Symposium (VTS)10.1109/VTS56346.2023.10140068(1-10)Online publication date: 24-Apr-2023
      • (2023)A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural NetworkIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.324138570:5(2085-2097)Online publication date: May-2023
      • (2022)Extreme Partial-Sum Quantization for Analog Computing-In-Memory Neural Network AcceleratorsACM Journal on Emerging Technologies in Computing Systems10.1145/352810418:4(1-19)Online publication date: 13-Oct-2022
      • (2021)Neural Network Training Acceleration With RRAM-Based Hybrid SynapsesFrontiers in Neuroscience10.3389/fnins.2021.69041815Online publication date: 24-Jun-2021
      • (2021)Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474056(856-861)Online publication date: 1-Feb-2021
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      • (2021)Stochastic SOT device based SNN architecture for On-chip Unsupervised STDP LearningIEEE Transactions on Computers10.1109/TC.2021.3119180(1-1)Online publication date: 2021
      • (2021)Quarry: Quantization-based ADC Reduction for ReRAM-based Deep Neural Network Accelerators2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643502(1-7)Online publication date: 1-Nov-2021
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