research-article

Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories

Authors:

Christophe Layer,

Laurent Becker,

Sylvain Claireux,

Guillaume Prenat,

Gregory Di Pendina,

Virgile Javerliac,

Fabrice Bernard-Granger,

Loic DecloedtAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 12, Issue 4

Article No.: 32, Pages 1 - 24

https://doi.org/10.1145/2876507

Published: 12 May 2016 Publication History

Abstract

The most widely used embedded memory technology, static random access memory (SRAM), is heading toward scaling problems in advanced technology nodes due to the leakage currents caused by the quantum tunneling effect. As an alternative, spin-transfer torque magnetic RAM (STT-MRAM) technology shows comparable performance in terms of speed and power consumption and much better performance in terms of density and leakage. Moreover, MRAM brings up new paradigms in system design thanks to its inherent nonvolatility, which allows the definition of new instant-on/off policies and leakage current optimization. Based on our compact model, we have developed a fully characterized system-on-chip from the basic cell up to the system architecture in a 40nm LP hybrid CMOS/magnetic process. Through simulations, first we demonstrate that STT-MRAM is a candidate for the memory part of embedded systems, and second we implement a check-pointing methodology based on the regular interrupt routines of a processor to enable a fast power on and off functionality. Using a synthetic benchmark developed in high-level programming languages intended to be representative of integer system performance, our method shows that having MRAM instead of SRAM in an embedded design brings up important energy savings. The influence of the check-pointing routine on power consumption is finally evaluated with regard to various shutdown and restart behaviors.

References

[1]

L. Berger. 1996. Emission of spin waves by a magnetic multilayer traversed by a current. Physical Review B 54, 13, 9353--9358.

[2]

Fabrice Bernard-Granger, Bernard Dieny, Raphael Fascio, and Kotb Jabeur. 2015. SPITT: A magnetic tunnel junction SPICE compact model for STT-MRAM. In Proceedings of the MOS-AK Workshop of the Design and Test in Europe Conference (DATE’15). http://www.mosak.org/grenoble_2015/presentations/T5_Bernard-Granger_MOS-AK_Grenoble_2015.pdf.

[3]

Mark Bohr. 2009. The new era of scaling in an SoC world. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC’09). 23--28.

[4]

John Carter and Karthick Rajamani. 2010. Designing energy-efficient servers and data centers. IEEE Transactions on Computers 43, 7, 76--78.

Digital Library

[5]

Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, and Bruce Jacob. 2013. Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. In Proceedings of the 19th International Symposium on High Performance Computer Architecture (HPCA’13). 143--154.

Digital Library

[6]

Joan Daemen and Vincent Rijmen. 2001. Announcing the advanced encryption standard (AES). In Federal Information Processing Standards, Publication 197. U.S. National Institute of Standards and Technology (NIST).

[7]

Grégory Di Pendina, Guillaume Prenat, Bernard Dieny, and Kholdun Torki. 2012. A hybrid magnetic/complementary metal oxide semiconductor process design kit for the design of low-power logic circuits. Journal of Applied Physics 111,07E350.

[8]

Zhitao Diao, Zhanjie Li, Shengyuang Wang, Yunfei Ding, Alex Panchula, Eugene Chen, Lien-Chang Wang, and Yiming Huai. 2007. Spin-transfer torque switching in magnetic tunnel junctions and spin-transfer torque random access memory. Journal of Physics 19, 16, 165209.1--165209.13.

[9]

Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, and Keiko Abe. 2015. Technology trends and near-future applications of embedded STT-MRAM. In Proceedings of the IEEE International Memory Workshop (IMW’15). 1--5.

[10]

Kejie Huang and Rong Zhao. 2014. Low power computing using STT-MRAM. In Proceedings of the 2014 14th Non-Volatile Memory Technology Symposium (NVMTS’14). 1--6.

[11]

Kejie Huang, Rong Zhao, and Yong Lian. 2014. STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing. In Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’14). 31--36.

Digital Library

[12]

David A. Huffman. 1952. A method for the construction of minimum-redundancy codes. Proceedings of the IRE 40, 9, 1098--1102.

[13]

S. Ikeda, J. Hayakawa, Y. Ashizawa, Y. M. Lee, K. Miura, H. Hasegawa, M. Tsunoda, F. Matsukura, and H. Ohno. 2008. Tunnel magnetoresistance of 604&percnt; at 300K by suppression of Ta diffusion in CoFeBMgOCoFeB pseudo-spin-valves annealed at high temperature. Applied Physics Letters 93, 082508.

[14]

K. Ikegami, H. Noguchi, C. Kamata, M. Amano, Keiko Abe, K. Kushida, E. Kitagawa, T. Ochiai, N. Shimomura, S. Itai, D. Saida, C. Tanaka, A. Kawasumi, H. Hara, J. Ito, and S. Fujita. 2014. Low power and high density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integration and asymmetric compensation techniques. In Proceedings of the IEEE International Electron Devices Meeting (IEDM’14). 28.1.1--28.1.4.

[15]

Kotb Jabeur, Fabrice Bernard-Granger, Grégory Di Pendina, Guillaume Prenat, and Bernard Dieny. 2014. Comparison of Verilog-A compact modelling strategies for spintronic devices. IEEE Electronics Letters 50, 19, 1353--1355.

[16]

Asral B. Jambek and Nor A. Khairi. 2014. Performance comparison of Huffman and Lempel-Ziv Welch data compression for wireless sensor node application. American Journal of Applied Science 11, 1, 119--126.

[17]

A. V. Khvalkovskiy, D. Apalkov, S. Watts, R. Chepulskii, R. S. Beach, A. Ong, X. Tang, A. Driskill-Smith, W. H. Butler, P. B. Visscher, D. Lottis, E. Chen, V. Nikitin, and M. Krounbi. 2013. Basic principles of STT-MRAM cell operation in memory arrays. Journal of Applied Physics 46, 7, 074001.

[18]

Emre Kültürsay, Mahmut Kandemir, Anand Sivasubramaniam, and Onur Mutlu. 2013. Evaluating STT-RAM as an energy-efficient main memory alternative. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’13). 256--267.

[19]

Kon-Woo Kwon, Xuanyao Fong, Parami Wijesinghe, Priyadarshini Panda, and Kaushik Roy. 2015. High-density and robust STT-MRAM array through device/circuit/architecture interactions. IEEE Transactions on Nanotechnology 14, 6, 1024--1034.

Digital Library

[20]

Damjan Lampret, Chen-Min Chen, Marko Mlinar, Johan Rydberg, Matan Ziv-Av, Chris Ziomkowski, Greg McGary, and Bob Gardner. 2012. OpenRISC 1000 Architecture Manual, Version 1.0 rev. 0. Available at http://opencores.org/or1k.

[21]

Christophe Layer, Kotb Jabeur, Laurent Becker, Bernard Dieny, Stéphane Gros, Virgile Javerliac, Pierre Paoli, and Fabrice Bernard-Granger. 2015. Hybrid STT/CMOS design of an interrupt based instant on/off mechanism for low-power SoC. In Proceedings of the IEEE International Symposium on VLSI Systems (ISVLSI’15). 315--320.

[22]

Y. Lee, Y. Kim, D. Yoon, D. Blaauw, and D. Sylvester. 2012. Circuit and system design guidelines for ultra-low power sensor nodes. In Proceedings of the 49th ACM/EDAC/IEEE Design Automation Conference (DAC’12). 1037--1042.

Digital Library

[23]

Dong U. Lee, Hyungjin Kim, Mohammad Rahimi, Deborah Estrin, and John D. Villasenor. 2009. Energy-efficient image compression for resource-constrained platforms. IEEE Transactions on Image Processing 18, 9, 2100--2113.

Digital Library

[24]

Jianhua Li, Liang Shi, Qingan Li, Chun Jason Xue, Yiran Chen, and Wei Wang. 2013. Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh. ACM Transactions on Design Automation of Electronic Systems 19, 1, 1--23.

Digital Library

[25]

Jing Li, Charles Augustine, Sayeef Salahuddin, and Kaushik Roy. 2008. Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT-MRAM) array for yield enhancement. In Proceedings of the 45th ACM/IEEE Design Automation Conference (DAC’08). 278--283.

Digital Library

[26]

T. M. Maffitt, J. K. DeBrosse, J. A. Gabric, E. T. Gow, M. C. Lamorey, J. S. Parenteau, D. R. Willmott, M. A. Wood, and W. J. Gallagher. 2006. Design considerations for MRAM. IBM Journal of Research and Development 50, 1, 24--39.

Digital Library

[27]

Lauri Minas and Brad Ellison. 2009. The Problem of Power Consumption in Servers. Intel Press, Hillsboro, OR.

[28]

Sparsh Mittal, Jeffrey S. Vetter, and Dong Li. 2015. A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches. IEEE Transactions on Parallel and Distributed Systems 26, 6, 1524--1537.

Digital Library

[29]

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu. 2013. Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75&percnt; leakage reduction using cycle-based power gating. In Proceedings of the IEEE International Solid State Circuit Conference (ISSCC’13). 194--196.

[30]

Tsugio Noda, Masahiro Fukuda, Hirotaka Chiba, Kimitaka Murashita, Yoshinobu Komagata, and Masahiro Mori. 1991. A JPEG still picture compression LSI. In Proceedings of the IEEE Symposium on Very Large Scale Integrated Circuits (ISVLSI’91). 33--34.

[31]

Kumiko Nomura, Keiko Abe, Hiroaki Yoda, and Shinobu Fujita. 2012. Ultra-low power processor using perpendicular-STT-MRAM/SRAM based hybrid cache toward next generation normally-off computers. Journal of Applied Physics 111, 7, 07E330--07E330-3.

[32]

Fabian Oboril, Rajendra Bishnoi, Mojtaba Ebrahimi, and Mehdi B. Tahoori. 2015. Evaluation of hybrid memory technologies using SOT-MRAM for on-chip cache hierarchy. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, 3, 367--380.

Digital Library

[33]

Jean-Michel Portal, Marc Bocquet, Mathieu Moreau, Hassen Aziza, Damien Deleruyelle, Yue Zhang, Wang Kang, Jacques-Olivier Klein, Claude Chappert, and Wei-Sheng Zhao. 2014. An overview of non-volatile flip-flops based on emerging memory technologies. Journal of Electronic Science and Technology 12, 2, 173--181.

[34]

Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, and Sudhakar Yalamanchili. 2010. An energy efficient cache design using spin torque transfer (STT) RAM. In Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’10). 389--394.

Digital Library

[35]

Greg Roelofs. 1999. IEC Standard 1999. Retrieved March 30, 2016, from http://www.libpng.org/pub/png.

[36]

Christopher M. Sadler and Margaret Martonosi. 2006. Data compression algorithms for energy-constrained devices in delay tolerant networks. In Proceedings of the 4th International Conference on Embedded Networked Sensor Systems (SenSys’06). 265--278.

Digital Library

[37]

Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, and Naoki Kasai. 2008. Nonvolatile magnetic flip-flop for standby-power-free SoCs. In Proceedings of the IEEE Custom Integrated Circuits Conference (CICC’08). 355--358.

[38]

John C. Slonczewski. 1996. Current-driven excitation of magnetic multilayers. Journal of Magnetism and Magnetic Materials 159, L1--L7.

[39]

John C. Slonczewski and Jonathan Z. Sun. 2007. Theory of voltage-driven current and torque in magnetic tunnel junctions. Journal of Magnetism and Magnetic Materials 310, 169--175.

[40]

Jianwen Sun, Xiang Long, Han Wan, and Jingwei Yang. 2014. A checkpointing and instant-on mechanism for an embedded system based on non-volatile memories. In Proceedings of the IEEE International Conference on Computer Communications (INFOCOM’14). 173--178.

[41]

Jonathan Z. Sun. 2000. Spin-current interaction with a monodomain magnetic body: A model study. Physical Review B 62, 1, 570--578.

[42]

Zhenyu Sun, Xiuyuan Bi, Hai Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, and Wenqing Wu. 2011. Multi retention level STT-RAM cache designs with a dynamic refresh scheme. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-44). 329--338.

Digital Library

[43]

Luis Vitorio Cargnini, Lionel Torres, Raphael M. Brum, Sophiane Senni, and Gilles Sassatelli. 2014. Embedded memory hierarchy exploration based on magnetic random access memory. Journal of Low Power Electronics and Applications 4, 3, 214--230.

[44]

Thomas Vogelsang. 2010. Understanding the energy consumption of dynamic random access memories. In Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture(MICRO-43). 363--374.

Digital Library

[45]

Xiaobin Wang, Yuankai Zheng, Haiwen Xi, and Dimitar Dimitrov. 2008. Thermal fluctuation effects on spin torque induced switching: Mean and variations. Journal of Applied Physics 103, 3, 034507.

[46]

Wei Wei, Kazuteru Namba, Jie Han, and Fabrizio Lombardi. 2014. Design of a nonvolatile 7T1R SRAM cell for instant-on operation. IEEE Transactions on Nanotechnologies 13, 5, 905--916.

[47]

Jiang Xiao, Andrew Zangwill, and Mark D. Stiles. 2004. Boltzmann test of Slonczewski’s theory of spin-transfer torque. In Physical Review B 70, 172405.

[48]

Yun Ye, Frank Liu, Min Chen, Sani Nassif, and Yu Cao. 2011. Statistical modeling and simulation of threshold variation under random dopant fluctuations and line-edge roughness. IEEE Transactions on Very Large Scale Integration Systems 19, 6, 987--996.

Digital Library

[49]

H. Yoda, S. Fujita, N. Shimomura, E. Kitagawa, K. Abe, K. Nomura, H. Noguchi, and J. Ito. 2012. Progress of STT-MRAM technology and the effect on normally-off computing systems. In Proceedings of the IEEE International Electron Devices Meetings (IEDM’12). 1131--1134.

[50]

Jacob Ziv and Abraham Lempel. 1977. A universal algorithm for sequential data compression. IEEE Transactions on Information Theory 23, 3, 337--343.

Digital Library

Cited By

Senni SDelobelle TCoi OPeneau PTorres LGamatie ABenoit PSassatelli G(2017)Embedded systems to high performance computing using STT-MRAMProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130502(536-541)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130502
Senni SDelobelle TCoi OPeneau PTorres LGamatie ABenoit PSassatelli G(2017)Embedded systems to high performance computing using STT-MRAMDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927046(536-541)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927046
Senni STorres LBenoit PGamatie ASassatelli G(2017)Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power, and Reliable DevicesIEEE Magnetics Letters10.1109/LMAG.2017.27127808(1-5)Online publication date: 2017
https://doi.org/10.1109/LMAG.2017.2712780
Show More Cited By

Index Terms

Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories
1. Computer systems organization
  1. Embedded and cyber-physical systems
    1. System on a chip
2. Hardware

Recommendations

Advanced Low Power Spintronic Memories beyond STT-MRAM
GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

Until now, spin transfer torque magnetic random access memory (STT-MRAM) has drawn considerable R&D interest worldwide. A number of companies and universities are currently involved in this promising technology. In 2016, Everspin released the first 256M ...
Review of physics-based compact models for emerging nonvolatile memories

A generic compact modeling methodology for emerging nonvolatile memories is proposed by coupling comprehensive physical equations from multiple domains (e.g., electrical, thermal, magnetic, phase transitions). This concept has been applied to three most ...
Modeling Power Consumption of NAND Flash Memories Using FlashPower

Flash is the most popular solid-state memory technology used today. A range of consumer electronics products, such as cell-phones and music players, use flash memory for storage and flash memory is increasingly displacing hard disk drives as the primary ...

Comments

Information & Contributors

Information

Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 12, Issue 4

Regular Papers

July 2016

394 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/2856147

Editor:
Yuan Xie
University of California, Santa Barbara, USA

Issue’s Table of Contents

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 12 May 2016

Accepted: 01 January 2016

Revised: 01 December 2015

Received: 01 September 2015

Published in JETC Volume 12, Issue 4

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Funding Sources

ERC
European Union under the European Research Council (ERC)

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
265
Total Downloads

Downloads (Last 12 months)5
Downloads (Last 6 weeks)1

Reflects downloads up to 06 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Senni SDelobelle TCoi OPeneau PTorres LGamatie ABenoit PSassatelli G(2017)Embedded systems to high performance computing using STT-MRAMProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130502(536-541)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130502
Senni SDelobelle TCoi OPeneau PTorres LGamatie ABenoit PSassatelli G(2017)Embedded systems to high performance computing using STT-MRAMDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927046(536-541)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927046
Senni STorres LBenoit PGamatie ASassatelli G(2017)Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power, and Reliable DevicesIEEE Magnetics Letters10.1109/LMAG.2017.27127808(1-5)Online publication date: 2017
https://doi.org/10.1109/LMAG.2017.2712780
Peneau PBouziane RGamatie ARohou EBruguier FSassatelli GTorres LSenni S(2016)Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2016.7833682(162-169)Online publication date: Sep-2016
https://doi.org/10.1109/PATMOS.2016.7833682

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents