Article

A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation

Authors:

Carl TropperAuthors Info & Claims

PADS '07: Proceedings of the 21st International Workshop on Principles of Advanced and Distributed Simulation

Pages 211 - 218

https://doi.org/10.1109/PADS.2007.4

Published: 12 June 2007 Publication History

Abstract

Many partitioning algorithms have been proposed for distributed VLSI simulation. Typically, they make use of a gate level netlist, and attempt to achieve a minimal cut size subject to a load balance constraint. The algorithm executes on a hypergraph which represents the netlist. In this paper we propose a design-driven iterative partitioning algorithm for Verilog based on module instances instead of gates. We do this in order to take advantage of the design hierarchy information contained in the modules and their instances. A Verilog instance represents one vertex in the circuit hypergraph. The vertex can be flattened into multiple vertices in the event that a load balance is not achieved by instance based partitioning. In this case the algorithm flattens the largest instance and moves gates between the partitions in order to improve the load balance. Our experiments show that this partitioning algorithm produces a smaller cutsize than is produced by hmetis on a gate-level netlist. It produces better speedup for the simulation because it takes advantage of the design hierarchy.

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Cited By

Eker AArafa YBadawy ASanthi NEidenbenz SPonomarev DDiallo STolk AGiabbanelli P(2021)Load-Aware Dynamic Time Synchronization in Parallel Discrete Event SimulationProceedings of the 2021 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation10.1145/3437959.3459249(95-105)Online publication date: 21-May-2021
https://dl.acm.org/doi/10.1145/3437959.3459249
Yang SHan JKwak DKim NCha DPark JKim JFettweis GNebel W(2014)Predictive parallel event-driven HDL simulation with a new powerful prediction strategyProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617060(1-3)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2617060
Ahmad TCiesielski MFettweis GNebel W(2014)Fast STA prediction-based gate-level timing simulationProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616977(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616977
Show More Cited By

Index Terms

A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation
  2. Integrated circuits
    1. Logic circuits

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Published In

cover image ACM Conferences

PADS '07: Proceedings of the 21st International Workshop on Principles of Advanced and Distributed Simulation

June 2007

208 pages

ISBN:0769528988

Sponsors

SIGSIM: ACM Special Interest Group on Simulation and Modeling

Publisher

IEEE Computer Society

United States

Publication History

Published: 12 June 2007

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Conference

PADS07

Sponsor:

SIGSIM

PADS07: PADS '07 - Principles of Advanced and Distributed Simulation

June 12 - 15, 2007

Acceptance Rates

PADS '07 Paper Acceptance Rate 24 of 37 submissions, 65%;

Overall Acceptance Rate 398 of 779 submissions, 51%

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Cited By

Eker AArafa YBadawy ASanthi NEidenbenz SPonomarev DDiallo STolk AGiabbanelli P(2021)Load-Aware Dynamic Time Synchronization in Parallel Discrete Event SimulationProceedings of the 2021 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation10.1145/3437959.3459249(95-105)Online publication date: 21-May-2021
https://dl.acm.org/doi/10.1145/3437959.3459249
Yang SHan JKwak DKim NCha DPark JKim JFettweis GNebel W(2014)Predictive parallel event-driven HDL simulation with a new powerful prediction strategyProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617060(1-3)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2617060
Ahmad TCiesielski MFettweis GNebel W(2014)Fast STA prediction-based gate-level timing simulationProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616977(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616977
Wang JBahulkar KPonomarev DAbu-Ghazaleh NLoper MWainer G(2013)Can PDES scale in environments with heterogeneous delays?Proceedings of the 1st ACM SIGSIM Conference on Principles of Advanced Discrete Simulation10.1145/2486092.2486098(35-46)Online publication date: 19-May-2013
https://dl.acm.org/doi/10.1145/2486092.2486098
Bahulkar KWang JAbu-Ghazaleh NPonomarev D(2012)Partitioning on Dynamic Behavior for Parallel Discrete Event SimulationProceedings of the 2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation10.1109/PADS.2012.32(221-230)Online publication date: 15-Jul-2012
https://dl.acm.org/doi/10.1109/PADS.2012.32
Jagtap DBahulkar KPonomarev DAbu-Ghazaleh N(2012)Characterizing and Understanding PDES Behavior on Tilera ArchitectureProceedings of the 2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation10.1109/PADS.2012.10(53-62)Online publication date: 15-Jul-2012
https://dl.acm.org/doi/10.1109/PADS.2012.10
Lijun Li Tropper C(2009)A Multiway Design-driven Partitioning Algorithm for Distributed Verilog SimulationSimulation10.1177/003754970910276085:4(257-270)Online publication date: 1-Apr-2009
https://dl.acm.org/doi/10.1177/0037549709102760
Xu QTropper C(2009)On Determining How Many Computers to Use in Parallel VLSI SimulationProceedings of the 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation10.1109/PADS.2009.18(122-128)Online publication date: 22-Jun-2009
https://dl.acm.org/doi/10.1109/PADS.2009.18

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