Article

Parallel Logic Simulation of Million-Gate VLSI Circuits

Authors:

Lijuan Zhu,

Gilbert Chen,

Boleslaw K. Szymanski,

Carl Tropper,

Tong ZhangAuthors Info & Claims

MASCOTS '05: Proceedings of the 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems

Pages 521 - 524

Published: 27 September 2005 Publication History

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Abstract

The complexity of today s VLSI chip designs makes veri fication a necessary step before fabrication. As a result, gate-level logic simulation has became an integral component of the VLSI circuit design process which verifies the design and analyzes its behavior. Since the designs constantly grow in size and complexity, there is a need for ever more ef__ __cient simulations to keep the gate-level logic veri- fication time acceptably small. The focus of this paper is an efficient simulation of large chip designs. We present the design and implementation of a new parallel simulator, called DSIM, and demonstrate DSIM s efficiency and speed by simulating a million gate circuit using different numbers of processors.

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Poshtkohi AGhaznavi-Ghoushchi MSaghafi K(2019)Optimistic Modeling and Simulation of Complex Hardware Platforms and Embedded Systems on Many-Core HPC ClustersIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2018.286001430:2(428-444)Online publication date: 1-Feb-2019
https://dl.acm.org/doi/10.1109/TPDS.2018.2860014
Poshtkohi AGhaznavi-Ghoushchi MSaghafi K(2019)PSMLThe Journal of Supercomputing10.1007/s11227-018-2682-175:5(2691-2724)Online publication date: 1-May-2019
https://dl.acm.org/doi/10.1007/s11227-018-2682-1
Moffitt MSustik MVillarrubia PStok LDutt NHassoun S(2011)Robust partitioning for hardware-accelerated functional verificationProceedings of the 48th Design Automation Conference10.1145/2024724.2024915(854-859)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024915
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Index Terms

Parallel Logic Simulation of Million-Gate VLSI Circuits
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies
2. Hardware

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MASCOTS '05: Proceedings of the 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems

September 2005

523 pages

ISBN:0769524583

Publisher

IEEE Computer Society

United States

Publication History

Published: 27 September 2005

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Cited By

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Poshtkohi AGhaznavi-Ghoushchi MSaghafi K(2019)Optimistic Modeling and Simulation of Complex Hardware Platforms and Embedded Systems on Many-Core HPC ClustersIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2018.286001430:2(428-444)Online publication date: 1-Feb-2019
https://dl.acm.org/doi/10.1109/TPDS.2018.2860014
Poshtkohi AGhaznavi-Ghoushchi MSaghafi K(2019)PSMLThe Journal of Supercomputing10.1007/s11227-018-2682-175:5(2691-2724)Online publication date: 1-May-2019
https://dl.acm.org/doi/10.1007/s11227-018-2682-1
Moffitt MSustik MVillarrubia PStok LDutt NHassoun S(2011)Robust partitioning for hardware-accelerated functional verificationProceedings of the 48th Design Automation Conference10.1145/2024724.2024915(854-859)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024915
Li LTropper C(2007)A Design-Driven Partitioning Algorithm for Distributed Verilog SimulationProceedings of the 21st International Workshop on Principles of Advanced and Distributed Simulation10.1109/PADS.2007.4(211-218)Online publication date: 12-Jun-2007
https://dl.acm.org/doi/10.1109/PADS.2007.4

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Basic circuits for multi-valued sequential logic

Quaternary CMOS Combinational Logic Circuits

Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits

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