research-article

Deadlock-Free Message Routing in Multiprocessor Interconnection Networks

Authors:

C. L. SeitzAuthors Info & Claims

IEEE Transactions on Computers, Volume 36, Issue 5

Pages 547 - 553

https://doi.org/10.1109/TC.1987.1676939

Published: 01 May 1987 Publication History

Abstract

A deadlock-free routing algorithm can be generated for arbitrary interconnection networks using the concept of virtual channels. A necessary and sufficient condition for deadlock-free routing is the absence of cycles in a channel dependency graph. Given an arbitrary network and a routing function, the cycles of the channel dependency graph can be removed by splitting physical channels into groups of virtual channels. This method is used to develop deadlock-free routing algorithms for k-ary n-cubes, for cube-connected cycles, and for shuffle-exchange networks.

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Cited By

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Deadlock-Free Message Routing in Multiprocessor Interconnection Networks

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 36, Issue 5

May 1987

134 pages

ISSN:0018-9340

Editor:
Bruce D. Shriver

Issue’s Table of Contents

Copyright © 1987.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 May 1987

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Cited By

Basu PZhao LFantl JPal SKrishnamurthy AKhoury JMencagli GDazzi PLowenthal DBadia R(2024)Efficient all-to-all Collective Communication Schedules for Direct-connect TopologiesProceedings of the 33rd International Symposium on High-Performance Parallel and Distributed Computing10.1145/3625549.3658656(28-41)Online publication date: 3-Jun-2024
https://dl.acm.org/doi/10.1145/3625549.3658656
Mukosey ASemenov ATretiakov A(2024)Graph based routing algorithm for torus topology and its evaluation for the Angara interconnectJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.104765183:COnline publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1016/j.jpdc.2023.104765
Cao ZGuo WWan ZLi PLiu QWang CShao Y(2024)ETRS: efficient turn restrictions setting method for boundary routers in chiplet-based systemsThe Journal of Supercomputing10.1007/s11227-024-06261-z80:14(20488-20517)Online publication date: 1-Jun-2024
https://dl.acm.org/doi/10.1007/s11227-024-06261-z
Gomez-Lopez GEscudero-Sahuquillo JGarcia PQuiles F(2024)Implementation and testing of a KNS topology in an InfiniBand clusterThe Journal of Supercomputing10.1007/s11227-024-06214-680:14(21306-21338)Online publication date: 7-Jun-2024
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Yan JWang MQin YYu Z(2023)CRAFT: Common Router Architecture for Throughput OptimizationAlgorithms and Architectures for Parallel Processing10.1007/978-981-97-0798-0_13(212-229)Online publication date: 20-Oct-2023
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Liu JLi CYe Y(2022)A Path Utilization-Based Congestion-Aware Deadlock-Free Routing for Network-on-ChipProceedings of the 2022 6th International Conference on Electronic Information Technology and Computer Engineering10.1145/3573428.3573587(883-889)Online publication date: 21-Oct-2022
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