Congestion aware low power on chip protocols with network on chip with cloud security
Authors: 
Suresh Ponnan, Tikkireddi Aditya Kumar, Hemakumar VS, Sakthieswaran Natarajan, Mohd Asif ShahAuthors Info & Claims
Suresh Ponnan, Tikkireddi Aditya Kumar, Hemakumar VS, Sakthieswaran Natarajan, Mohd Asif ShahAuthors Info & ClaimsAbstract
This article is to analyze the bottleneck problems of NoC in many more applications like multi-processor communication, computer architectures, and network interface processors. This paper aims to research the advantages and disadvantages of low congestion protocols on highway environments like multiple master multiple slave interconnections. A long-term evolution and effective on-chip connectivity solution for secured, congestion aware and low power architecture is emerged for Network-on-Chip (NoC) for MCSoC. Applications running simultaneously on a different chip are often exchanged dynamically on the chip network. Of-course, in general on chip communication, resources mean that applications may interact with shared resources to influence each other's time characteristics.
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Published: 09 September 2022
Accepted: 03 August 2022
Received: 23 June 2022
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