Congestion aware low power on chip protocols with network on chip with cloud security
Abstract
References
Recommendations
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors
CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesisIncreasing application complexity and improvements in process technology have today enabled chip multiprocessors (CMPs) with tens to hundreds of cores on a chip. Networks on Chip (NoCs) have emerged as scalable communication fabrics that can support ...
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip
ISVLSI '09: Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSINetworks-on-chip (NoCs) can improve the communication bandwidth and power efficiency of multiprocessor systems-on-chip (MPSoC). However, traditional metallic interconnects consume significant amount of power to deliver even higher communication ...
A design flow for an optimized congestion-aware application-specific wireless network-on-chip architecture
AbstractWireless Networks-on-Chip (WiNoC) architecture has emerged as an alternative communication infrastructure for the conventional wire-line NoC to achieve higher performance and low energy dissipation in on-chip communications. However, ...
Highlights- A novel WiNoC architecture is proposed based on a new MoT topology for future chip multiprocessors.
Comments
Information & Contributors
Information
Published In
Publisher
Hindawi Limited
London, United Kingdom
Publication History
Author Tags
Qualifiers
- Research-article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Other Metrics
Citations
View Options
View options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in