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A generic architecture for on-chip packet-switched interconnections

Authors:

Pierre Guerrier,

Alain GreinerAuthors Info & Claims

DATE '00: Proceedings of the conference on Design, automation and test in Europe

Pages 250 - 256

https://doi.org/10.1145/343647.343776

Published: 01 January 2000 Publication History

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A generic architecture for on-chip packet-switched interconnections
1. Hardware

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DATE '00: Proceedings of the conference on Design, automation and test in Europe

January 2000

707 pages

ISBN:1581132441

DOI:10.1145/343647

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Published: 01 January 2000

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Dinesh Kumar TKarthikeyan A(2023)Dynamic low power management technique for decision directed inter-layer communication in three dimensional wireless network on chipAutomatika10.1080/00051144.2023.226108864:4(1280-1295)Online publication date: 6-Oct-2023
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A hybrid packet-circuit switched on-chip network based on SDM

Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs

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