research-article

Feasibility of Embedded DRAM Cells on FinFET Technology

Authors:

Antonio Calomarde,

Antonio RubioAuthors Info & Claims

IEEE Transactions on Computers, Volume 65, Issue 4

Pages 1068 - 1074

https://doi.org/10.1109/TC.2014.2375204

Published: 01 April 2016 Publication History

Abstract

In this paper, we analyze the suitability of implementing embedded DRAM (eDRAM) cells on FinFET technology compared to classical planar MOSFETs. The results show a significant improvement in overall cell performance for multi-gate devices. While pFinFET-based memories showed better cell behavior and variability robustness, mixed n/pFinFET cells had the highest working frequency and a negligible impact on degradation. Finally, we show that a multiple fin-height strategy can be used to reduce the layout area of the eDRAM cells (>10%).

References

[1]

W. Haensch, E. J. Nowak, R. H. Dennard, P. M. Solomon, A. Bryant, O. H. Dokumaci, A. Kumar, X. Wang, J. B. Johnson, and M. V. Fischetti, “Silicon CMOS devices beyond scaling,” IBM J. Res. Develop., vol. 50, no. 4/5, pp. 339–361, 2006.

Digital Library

[2]

T. Matsukawa, S. O'uchi, K. Endo, Y. Ishikawa, H. Yamauchi, Y. X. Liu, J. Tsukada, K. Sakamoto, and M. Masahara, “Comprehensive analysis of variability sources of FinFET characteristics,” in Proc. Symp. VLSI Technol., 2009, pp. 118–119.

[3]

L. W. Massengill, B. L. Bhuva, W. T. Holman, M. L. Alles, and T. D. Loveless, “Technology scaling and soft error reliability,” in Proc. IEEE Int. Rel. Phys. Symp., 2012, pp. 3C.1.1– 3C.1.7.

[4]

R. Naseer, Y. Boulghassoul, J. Draper, S. Dasgupta, and A. Witulski, “Critical charge characterization for soft error rate modeling in 90 nm SRAM,” in Proc. IEEE Int. Symp. Circuits Syst., 2007, pp. 1879–1882.

[5]

N. Seifert, B. Gill, S. Jahinuzzaman, J. Basile, V. Ambrose, Q. Shi, R. Allmon, and A. Bramnik, “Soft error susceptibilities of 22 nm Tri-gate devices,” IEEE Trans. Nucl. Sci., vol. 59, no. 6, pp. 2666–2673, Dec. 2012.

[6]

S. Ramey, A. Ashutosh, C. Auth, J. Clifford, M. Hattendorf, J. Hicks, R. James, A. Rahman, V. Sharma, A. St Amour, and C. Wiegand, “Intrinsic transistor reliability improvements from 22 nm tri-gate technology,” in Proc. IEEE Int. Rel. Phys. Symp., 2013, pp. 4C.5.1–4C.5.5.

[7]

K. T. Lee, W. Kang, E. A. Chung, G. Kim, H. Shim, H. Lee, H. Kim, M. Choe, N. I. Lee, A. Patel, and J. Park, “Technology scaling on High-K & Metal-Gate FinFET BTI reliability,” in Proc. IEEE Int. Rel. Phys. Symp., 2013, pp. 2D.1.1–2D.1.4.

[8]

K. G. Anil, K. Henson, S. Biesemans, and N. Collaert, “Layout density analysis of FinFETs,” in Proc. Conf. Eur. Solid-State Device Res., 2003, pp. 139–142.

[9]

A. B. Sachid and C. Hu, “Denser and more stable SRAM using FinFETs with multiple fin heights,” IEEE Trans. Electron Devices, vol. 59, no. 8, pp. 2037 –2041, Aug. 2012.

[10]

W. K. Luk, J. Cai, R. H. Dennard, M. J. Immediato, and S. Kosonocky, “A 3-transistor DRAM cell with gated diode for enhanced speed and retention time,” in Proc. Symp. VLSI Circuits, 2006, pp. 184–185.

[11]

X. Liang, R. Canal, G. Y. Wei, and D. Brooks, “Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability,” IEEE Micro, vol. 28, no. 1, pp. 60–68, Jan./Feb. 2008.

Digital Library

[12]

K. C. Chun, P. Jain, J. H. Lee, and C. H. Kim, “A sub-0.9 V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias,” in Proc. Symp. VLSI Circuits, 2009, pp. 134–135.

[13]

A. Teman, P. Meinerzhagen, A. Burg, and A. Fish, “Review and classification of gain cell eDRAM implementations,” in Proc. IEEE 27th Conv. Electr. Electron. Eng. Israel, 2012, pp. 1–5.

[14]

K. C. Chun, P. Jain, T. H. Kim, and C. H. Kim, “A 667 MHz logic-compatible embedded DRAM featuring an asymmetric 2T gain cell for high speed on-die caches,” IEEE J. Solid-State Circuits, vol. 47, no. 2, pp. 547–559, Feb. 2012.

[15]

P. Meinerzhagen, A. Teman, A. Mordakhay, A. Burg, and A. Fish, “A sub-VT 2T gain-cell memory for biomedical applications,” in Proc. IEEE Subthreshold Microelectron. Conf., 2012, pp. 1–3.

[16]

M. T. Chang, P. T. Huang, and W. Hwang, “A 65 nm low power 2T1D embedded DRAM with leakage current reduction,” in Proc. IEEE Int. SOC Conf., 2007, pp. 207–210.

[17]

A. N. Bhoj and N. K. Jha, “Gated-diode FinFET DRAMs: Device and circuit design-considerations,” J. Emerg. Technol. Comput. Syst., vol. 6, no. 4, pp. 12:1 –12:32, 2010.

[18]

Z. Lu, J. G. Fossum, D. Sarkar, and Z. Zhou, “An ultra-fast floating-body/gate cell for embedded DRAM,” in Proc. IEEE SOI-3D-Subthreshold Microelectron. Technol. Unified Conf., 2013, pp. 1–2.

[19]

A. T. Do, H. Yi, K. S. Yeo, and T. T. Kim, “Retention time characterization and optimization of logic-compatible embedded DRAM cells,” in Proc. Asia Symp. Qual. Electron. Des., 2012, pp. 29–34.

[20]

Y. Lee, M. T. Chen, J. Park, D. Sylvester, and D. Blaauw, “A 5.42 nW/kB retention power logic-compatible embedded DRAM with 2T dual-Vt gain cell for low power sensing applications,” in Proc. IEEE Asian Solid State Circuits Conf. , 2010, pp. 1–4.

[21]

E. Amat, C. G. Almudever, N. Aymerich, R. Canal, and A. Rubio, “Impact of FinFET technology introduction in the 3T1D-DRAM memory cell,” IEEE Trans. Device Mater. Rel., vol. 13, no. 1, pp. 287–292, Mar. 2013.

[22]

K. C. Chun, P. Jain, T. H. Kim, and C. H. Kim, “A 1.1 V, 667 MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110usec,” in Proc. IEEE Symp. VLSI Circuits, 2010, pp. 191–192.

[23]

Synopsys, “HSPICE 2012.06, User Guide,” 2012.

[24]

S. Sinha, G. Yeric, V. Chandra, B. C, and Y. Cao, “Exploring sub-20 nm FinFET designs with predictive technology models,” in Proc. Des. Autom. Conf., 2012, pp. 283– 288.

[25]

Predictive technology models (PTM).(2012). [Online] Http://ptm.asu.edu

[26]

E. Amat, C. G. Almudever, N. Aymerich, R. Canal, and A. Rubio, “Variability mitigation mechanisms in scaled 3T1D DRAM memories to 22 nm and beyond,” IEEE Trans. Device Mater. Rel., vol. 13, no. 1, pp. 103–109, Mar. 2013.

[27]

T. Heijmen, D. Giot, and P. Roche, “Factors that impact the critical charge of memory elements,” in Proc. IEEE Int. On-Line Test. Symp. , 2006, pp. 57–62.

[28]

D. Munteanu and J. L. Autran, “Modeling and simulation of single-event effects in digital devices and ICs,” IEEE Trans. Nucl. Sci., vol. 55, no. 4, pp. 1854 –1878, Aug. 2008.

[29]

E. Amat, A. Calomarde, C. G. Almudever, N. Aymerich, R. Canal, and A. Rubio, “Impact of FinFET and III-V/Ge technology on logic and memory cell behavior,” IEEE Trans. Device Mater. Rel., vol. 14, no. 1, pp. 344–350, Mar. 2014.

[30]

Y. K. Choi, T. J. King, and C. Hu, “A spacer patterning technology for nanoscale CMOS,” IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 436–441, Mar. 2002.

[31]

T. Chiarella, L. Witters, A. Mercha, C. Kerner, M. Rakowski, C. Ortolland, L. Ragnarsson, B. Parvais, A. De Keersgieter, S. Kubicek, A. Redolfi, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, and T. Hoffmann, “Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession,” Solid. State. Electron., vol. 54, no. 9, pp. 855–860, Sep. 2010.

[32]

K. Lovin, B. C. Lee, X. Liang, D. Brooks, and G. Y. Wei, “Empirical performance models for 3T1D memories,” in Proc. IEEE Int. Conf. Comput. Des., 2009, pp. 398– 403.

[33]

K. Schuegraf, M. C. Abraham, A. Brand, M. Naik, and R. Thakur, “Semiconductor Logic Technology Innovation to Achieve Sub-10 nm Manufacturing,” IEEE J. Electron Devices Soc., vol. 1, no. 3, pp. 66–75, Mar. 2013.

Cited By

Seyedzadeh Sany BEbrahimi B(2022)FinFET based ultra-low power 3T GC-eDRAM with very high retention time in sub-22 nmAnalog Integrated Circuits and Signal Processing10.1007/s10470-022-02052-9113:1(27-39)Online publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1007/s10470-022-02052-9
Sadredini ERahimi RVerma VStan MSkadron K(2019)eAPProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358324(87-99)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358324

Index Terms

Feasibility of Embedded DRAM Cells on FinFET Technology
1. Applied computing
2. Hardware

Index terms have been assigned to the content through auto-classification.

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 65, Issue 4

April 2016

331 pages

ISSN:0018-9340

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Copyright © 2014.

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IEEE Computer Society

United States

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Published: 01 April 2016

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Cited By

Seyedzadeh Sany BEbrahimi B(2022)FinFET based ultra-low power 3T GC-eDRAM with very high retention time in sub-22 nmAnalog Integrated Circuits and Signal Processing10.1007/s10470-022-02052-9113:1(27-39)Online publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1007/s10470-022-02052-9
Sadredini ERahimi RVerma VStan MSkadron K(2019)eAPProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358324(87-99)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358324

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