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A Simple Yet Effective Technique for Global Wiring

Published: 01 November 2006 Publication History

Abstract

A simple algorithm to perform global wiring is described. Repeated iterations of the algorithm tend to improve the quality of wiring by rerouting around congested areas. Various parameters can be set to give preference to short routes or to reduce the time taken by the algorithm. The algorithm has been tried out for several master-slice chips containing up to 3500 cells with good results. The technique is easily extended to standard cell chip design. An implementation for global wiring of a structured custom chip design style is described along with results. The technique is adaptable to higher level packaging such as chips on modules or modules on a board.

Cited By

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  • (2017)PCB Escape Routing and Layer Minimization for Digital Microfluidic BiochipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.256819936:1(69-82)Online publication date: 1-Jan-2017
  • (2016)Power- and performance-efficient cluster-based network-on-chip with reconfigurable topologyMicroprocessors & Microsystems10.1016/j.micpro.2016.03.00446:PB(122-135)Online publication date: 1-Oct-2016
  • (2012)A coarse-grained reconfigurable architecture with compilation for high performanceInternational Journal of Reconfigurable Computing10.1155/2012/1635422012(3-3)Online publication date: 1-Jan-2012
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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 6, Issue 2
November 2006
138 pages

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IEEE Press

Publication History

Published: 01 November 2006

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Cited By

View all
  • (2017)PCB Escape Routing and Layer Minimization for Digital Microfluidic BiochipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.256819936:1(69-82)Online publication date: 1-Jan-2017
  • (2016)Power- and performance-efficient cluster-based network-on-chip with reconfigurable topologyMicroprocessors & Microsystems10.1016/j.micpro.2016.03.00446:PB(122-135)Online publication date: 1-Oct-2016
  • (2012)A coarse-grained reconfigurable architecture with compilation for high performanceInternational Journal of Reconfigurable Computing10.1155/2012/1635422012(3-3)Online publication date: 1-Jan-2012
  • (2010)Effect of serialized routing resources on the implementation area of datapath circuits on FPGASWSEAS Transactions on Computers10.5555/2001196.20011999:12(1401-1414)Online publication date: 1-Dec-2010
  • (2008)Optimal routing algorithms for rectilinear pin clusters in high-density multichip modulesACM Transactions on Design Automation of Electronic Systems10.1145/1391962.139197613:4(1-20)Online publication date: 3-Oct-2008
  • (2008)The coming of age of (academic) global routingProceedings of the 2008 international symposium on Physical design10.1145/1353629.1353662(148-155)Online publication date: 13-Apr-2008
  • (2007)Simultaneous shield and buffer insertion for crosstalk noise reduction in global routingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89864115:6(624-636)Online publication date: 1-Jun-2007
  • (2007)Reconfigurable ComputingundefinedOnline publication date: 2-Nov-2007
  • (2006)Trunk decomposition based global routing optimizationProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233597(472-479)Online publication date: 5-Nov-2006
  • (2006)Temperature-aware routing in 3D ICsProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118377(309-314)Online publication date: 24-Jan-2006
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