A coarse-grained reconfigurable architecture with compilation for high performance
Authors: 
Lu Wan, Chen Dong, Deming ChenAuthors Info & Claims
Lu Wan, Chen Dong, Deming ChenAuthors Info & ClaimsArticle No.: 3, Page 3
Abstract
We propose a fast data relay (FDR) mechanism to enhance existing CGRA (coarse-grained reconfigurable architecture). FDR can not only provide multicycle data transmission in concurrent with computations but also convert resource-demanding inter-processing-element global data accesses into local data accesses to avoid communication congestion. We also propose the supporting compiler techniques that can efficiently utilize the FDR feature to achieve higher performance for a variety of applications. Our results on FDR-based CGRA are compared with two other works in this field: ADRES and RCP. Experimental results for various multimedia applications show that FDR combined with the new compiler deliver up to 29% and 21% higher performance than ADRES and RCP, respectively.
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- A coarse-grained reconfigurable architecture with compilation for high performance
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Accepted: 09 January 2012
Revised: 05 January 2012
Published: 01 January 2012
Received: 05 October 2011
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