research-article

Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs

Authors:

Roberto Cordone,

Francesco Redaelli,

Massimo Antonio Redaelli,

Marco Domenico Santambrogio,

Donatella SciutoAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 28, Issue 5

Pages 662 - 675

https://doi.org/10.1109/TCAD.2009.2015739

Published: 01 May 2009 Publication History

Abstract

This paper proposes a new model for the partitioning and scheduling of a specification on partially dynamically reconfigurable hardware. Although this problem can be solved optimally only by tackling its subproblems jointly, the exceeding complexity of such a task leads to a decomposition into two phases. The partitioning phase is based on a new graph-theoretic approach, which aims to obtain near optimality even if performed independently from the subsequent phase. For the scheduling phase, a new integer linear programming formulation and a heuristic approach are developed. Both take into account configuration prefetching and module reuse. The experimental results show that the proposed method compares favorably with existing solutions.

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Cited By

Ding BHuang JWang JXu QChen SKang Y(2023)Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous ResourcesACM Transactions on Design Automation of Electronic Systems10.1145/362529528:6(1-26)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3625295
Mandava MReckamp PChen DSolihin YHeinrich M(2023)Nimblock: Scheduling for Fine-grained FPGA Sharing through VirtualizationProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589095(1-13)Online publication date: 17-Jun-2023
https://dl.acm.org/doi/10.1145/3579371.3589095
Ding BHuang JXu QWang JChen SKang Y(2023)Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable SystemsACM Transactions on Design Automation of Electronic Systems10.1145/353496828:1(1-21)Online publication date: 20-Jan-2023
https://dl.acm.org/doi/10.1145/3534968
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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 28, Issue 5

May 2009

168 pages

ISSN:0278-0070

Issue’s Table of Contents

Copyright © 2009.

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IEEE Press

Publication History

Published: 01 May 2009

Revised: 09 July 2008

Received: 27 November 2007

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Cited By

Ding BHuang JWang JXu QChen SKang Y(2023)Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous ResourcesACM Transactions on Design Automation of Electronic Systems10.1145/362529528:6(1-26)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3625295
Mandava MReckamp PChen DSolihin YHeinrich M(2023)Nimblock: Scheduling for Fine-grained FPGA Sharing through VirtualizationProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589095(1-13)Online publication date: 17-Jun-2023
https://dl.acm.org/doi/10.1145/3579371.3589095
Ding BHuang JXu QWang JChen SKang Y(2023)Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable SystemsACM Transactions on Design Automation of Electronic Systems10.1145/353496828:1(1-21)Online publication date: 20-Jan-2023
https://dl.acm.org/doi/10.1145/3534968
Dhar ARichter EYu MZuo WWang XKim NChen D(2022)DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAsIEEE Transactions on Computers10.1109/TC.2021.313778571:10(2577-2591)Online publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1109/TC.2021.3137785
Tang QWang ZGuo BZhu LWei J(2020)Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/340370213:3(1-24)Online publication date: 21-Aug-2020
https://dl.acm.org/doi/10.1145/3403702
Chen SHuang JXu XDing BXu Q(2019)Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288398239:1(199-212)Online publication date: 20-Dec-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2883982
da Silva BBraeken ADomínguez FTouhafi A(2018)Exploiting Partial Reconfiguration through PCIe for a Microphone Array Network EmulatorInternational Journal of Reconfigurable Computing10.1155/2018/32146792018Online publication date: 1-Jan-2018
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Xu XXu QHuang JChen SBehjat LHan JVelev MChen D(2017)An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAsProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060447(403-406)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3060403.3060447
Ramezani RSedaghat YClemente J(2017)Reliability Improvement of Hardware Task Graphs via Configuration Early FetchIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263172425:4(1408-1420)Online publication date: 1-Apr-2017
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Abdali EPelcat MBerry FDiguet JHeller D(2016)Task Clustering Approach to Optimize the Scheduling on a Partially Dynamically Reconfigurable FPGAs for image processing algorithmsProceedings of the 10th International Conference on Distributed Smart Camera10.1145/2967413.2974042(230-231)Online publication date: 12-Sep-2016
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