research-article

Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems

Authors:

Yi KangAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems, Volume 28, Issue 1

Article No.: 7, Pages 1 - 21

https://doi.org/10.1145/3534968

Published: 20 January 2023 Publication History

Abstract

Partially dynamic reconfiguration (PDR) technology can accelerate the reconfiguration process and overcome hardware resource constraints when facing the challenge of high performance with respect to applications and resources constraints on field-programmable gate arrays (FPGAs). On FPGAs with PDR technology, the available on-chip Block RAM (BRAM) resources may not satisfy the memory requirements for all data. If we reserve more BRAM resources, then the total area of the dynamically reconfigurable region (DRR) that is used for calculation will decrease, with a reduction in system performance. We propose a memory-aware optimization framework to search for the optimal solution considering partitioning, scheduling, and floorplanning, where we make a tradeoff between performance and on-chip memory resources utilization. We then propose methods for memory allocation: An ILP model and a heuristic algorithm are provided to determine the minimum memory requirements and the number of corresponding memory blocks for data, as well as to determine whether the memory block with its stored data is assigned on-chip or off-chip by formulating the problem into a 0-1 knapsack problem and solving it using dynamic programming. Experimental results show that the memory-aware optimization framework and methods of memory allocation can increase the amount of on-chip data access to 29.65% of the total data volume with guaranteed performance.

References

[1]

Chao Wang, Wenqi Lou, Lei Gong, Lihui Jin, Luchao Tan, Yahui Hu, Xi Li, and Xuehai Zhou. 2017. Reconfigurable hardware accelerators: Opportunities, trends, and challenges. arXiv preprint arXiv:1712.04771 (2017).

[2]

S. Hauck and A. Dehon. 2010. Reconfigurable Computing: The Theory and Practice of FPGA-based Computation. Morgan Kaufmann Publishers Inc.

[3]

X. Xu, X. Qi, J. Huang, and C. Song. 2017. An integrated optimization framework for partitioning, scheduling and floorplanning on partially dynamically reconfigurable FPGAs. In Proceedings of the Great Lakes Symposium on VLSI.

[4]

Y. Ma, Y. Cao, S. Vrudhula, and J. S. Seo. 2017. Optimizing loop operation and dataflow in FPGA acceleration of deep convolutional neural networks. In ACM/SIGDA International Symposium on Field-programmable Gate Arrays.

[5]

H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. 2003. Rectangle-packing-based module placement. The Best of ICCAD, Kuehlmann, A. (Ed.). Springer, Boston, MA.

[6]

M. R. Garey and D. S. Johnson. 1983. Computers and Intractability: A Guide to the Theory of NP-completeness. W. H. Freeman.

[7]

N. Liu, S. Chen, and T. Yoshimura. 2013. Resource-aware multi-layer floorplanning for partially reconfigurable FPGAs. In Proceeding of the 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines. IEEE, 252–255.

[8]

M. Rabozzi, A. Miele, and M. D. Santambrogio. 2015. Floorplanning for partially-reconfigurable FPGAs via feasible placements detection. IEEE (2015), 252–255.

[9]

Pritha Banerjee, Megha Sangtani, and Susmita Sur-Kolay. 2011. Floorplanning for partially reconfigurable FPGAs. IEEE Trans. Comput.-aid. Des. Integ. Circ. Syst. 30, 1 (2011), 8–17. DOI:

Digital Library

[10]

Roberto Cordone, Francesco Redaelli, Massimo Antonio Redaelli, Marco Domenico Santambrogio, and Donatella Sciuto. 2009. Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs. IEEE Trans. Comput.-aid. Des. Integ. Circ. Syst. 28, 5 (2009), 662–675.

Digital Library

[11]

A. Purgato, D. Tantillo, M. Rabozzi, D. Sciuto, and M. D. Santambrogio. 2016. Resource-efficient scheduling for partially-reconfigurable FPGA-based systems. In Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW’16).

[12]

P. H. Yuh, C. L. Yang, and Y. W. Chang, 2004. Temporal floorplanning using the T-tree formulation. In Proceeding of the IEEE/ACM International Conference on Computer Aided Design (ICCAD’04). IEEE, 300–305.

[13]

E. A. Deiana, M. Rabozzi, R. CaTtaneo, and M. D. Santambrogio. 2016. A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig’16).

[14]

Song Chen, Jinglei Huang, Xiaodong Xu, Bo Ding, and Qi Xu. 2020. Integrated optimization of partitioning, scheduling, and floorplanning for partially dynamically reconfigurable systems. IEEE Trans. Comput.-aid. Des. Integ. Circ. Syst. 39, 1 (2020), 199–212. DOI:

Digital Library

[15]

X. Zhang, J. Wang, Z. Chao, Y. Lin, and D. Chen. 2019. DNNBuilder: An automated tool for building high-performance DNN hardware accelerators for FPGAs. In Proceedings of the International Conference on Computer Aided Design (ICCAD’19).

[16]

X. Wei, Y. Liang, P. Zhang, C. H. Yu, and J. Cong. 2019. Overcoming data transfer bottlenecks in DNN accelerators via layer-conscious memory managment. In Proceedings of the ACM/SIGDA International Symposium.

Digital Library

[17]

K. Danne, 2004. Memory management to support multitasking on fpga based systems. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs. Vol. 21.

[18]

K. Danne. 2004. Operating systems for FPGA based computers and their memory management. In Proceedings of the ARCS—Organic Pervasive Computing, Workshops.

[19]

S. Yin, S. Tang, X. Lin, O. Peng, and S. Wei. 2018. A high throughput acceleration for hybrid neural networks with efficient resource management on FPGA. IEEE Trans. Comput.-aid. Des. Integ. Circ. Syst. PP, 99 (2018), 1–1.

[20]

L. Epstein and R. V. Stee. 2007. Improved results for a memory allocation problem. In Proceedings of the Workshop on Algorithms & Data Structures.

[21]

J. Park and W. Sung. 2016. FPGA based implementation of deep neural networks using on-chip memory only. In Proceedings of the IEEE International Conference on Acoustics.

Digital Library

[22]

D. Chen, J. Cong, and P. Pan. 2006. FPGA design automation: A survey. Foundations and Trends® in Electronic Design Automation 1, 3 (2006), 195–330. FPGA Design Automation: A Survey. FPGA Design Automation: A Survey.

Digital Library

[23]

Xilinx. 2020. Vivado Design Suite User Guide: Partial Reconfiguration. Retrieved from https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/.

[24]

Song Han, Huizi Mao, and William J. Dally. 2015. Deep compression: Compressing deep neural networks with pruning, trained quantization and Huffman coding. arXiv preprint arXiv:1510.00149 (2015).

[25]

Song Chen and Takeshi Yoshimura. 2008. Fixed-outline floorplanning: Enumerating block positions and a new objective function for calculating area costs. IEEE Trans. Comput.-aid. Des. 27, 5 (2008), 858–871.

Digital Library

[26]

R. P. Dick, D. L. Rhodes, and W. Wolf. 1998. TGFF: Task graphs for free. In Proceedings of the Sixth International Workshop on Hardware/Software Codesign (CODES/CASHE’98). IEEE, 97–101.

Digital Library

[27]

A. B. Kahng and I. L. Markov.2020. Vlsi Cad Bookshelf. Retrieved from http://vlsicad.eecs.umich.edu/BK.

[28]

I. Gurobi Optimization. 2015. Gurobi optimizer reference manual. Retrieved from http://www.gurobi.com.

Cited By

Alismail SKoch D(2023)Efficient Resource Scheduling for Runtime Reconfigurable Systems on FPGAs2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL60245.2023.00025(123-129)Online publication date: 4-Sep-2023
https://doi.org/10.1109/FPL60245.2023.00025

Index Terms

Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Partitioning and floorplanning

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 28, Issue 1

January 2023

321 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3573313

Editor:
X. Sharon Hu
University of Notre Dame, USA

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 20 January 2023

Online AM: 23 May 2022

Accepted: 01 May 2022

Revised: 28 March 2022

Received: 01 September 2021

Published in TODAES Volume 28, Issue 1

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National Key R&D Program of China
National Natural Science Foundation of China
CAS Project for Young Scientists in Basic Research
Strategic Priority Research Program of Chinese Academy of Sciences

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Cited By

Alismail SKoch D(2023)Efficient Resource Scheduling for Runtime Reconfigurable Systems on FPGAs2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL60245.2023.00025(123-129)Online publication date: 4-Sep-2023
https://doi.org/10.1109/FPL60245.2023.00025

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