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VeriTrust: Verification for Hardware Trust

Published: 01 July 2015 Publication History

Abstract

Today's integrated circuit designs are vulnerable to a wide range of malicious alterations, namely hardware Trojans (HTs). HTs serve as backdoors to subvert or augment the normal operation of infected devices, which may lead to functionality changes, sensitive information leakages, or denial of service attacks. To tackle such threats, this paper proposes a novel verification technique for hardware trust, namely VeriTrust, which facilitates to detect HTs inserted at design stage. Based on the observation that HTs are usually activated by dedicated trigger inputs that are not sensitized with verification test cases, VeriTrust automatically identifies such potential HT trigger inputs by examining verification corners. The key difference between VeriTrust and existing HT detection techniques based on “unused circuit identification” is that VeriTrust is insensitive to the implementation style of HTs. Experimental results show that VeriTrust is able to detect all HTs evaluated in this paper (constructed based on various HT design methodologies shown in this paper) at the cost of moderate extra verification time.

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        cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
        IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 34, Issue 7
        July 2015
        161 pages

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        IEEE Press

        Publication History

        Published: 01 July 2015

        Author Tags

        1. hardware trust
        2. Design verification
        3. hardware Trojan (HT)

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        • (2023)JinnProceedings of the 32nd USENIX Conference on Security Symposium10.5555/3620237.3620627(6965-6982)Online publication date: 9-Aug-2023
        • (2023)Hardware IP Assurance against Trojan Attacks with Machine Learning and Post-processingACM Journal on Emerging Technologies in Computing Systems10.1145/359279519:3(1-23)Online publication date: 21-Jun-2023
        • (2023)Static Probability Analysis Guided RTL Hardware Trojan Test GenerationProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3567921(510-515)Online publication date: 16-Jan-2023
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