research-article

Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory

Authors:

Jun ChengAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 41, Issue 10

Pages 3438 - 3451

https://doi.org/10.1109/TCAD.2021.3123288

Published: 01 October 2022 Publication History

Abstract

Owing to the effect of data retention noise in multi-level-cell NAND flash memory, the initial threshold-voltage distributions and read voltages can no longer be used to accurately calculate log-likelihood ratios (LLRs) as the retention time increases, thus causing retention errors. To solve this problem, we first utilize the so-called “correction factors” to optimize the LLR accuracy by maximizing the achievable rate of a flash-memory system without introducing extra memory-sensing operations. We further prove that the optimization of the correction factors is a convex optimization problem and can be solved analytically. To obtain the optimal correction factors, we propose two retention-error correction schemes, referred to as offline maximum-achievable-rate correction (MARC) algorithm and online MARC algorithm, which enable the flash-memory controller to utilize the corrected LLRs that are stored in a look-up table and correct the inaccurate LLRs in real time, respectively. Motivated by the variation characteristics of the threshold-voltage distributions, we also propose an enhanced expectation–maximization (EM) algorithm to reestimate their corresponding parameters, and then adjust the read voltages. By combining the enhanced EM algorithm with the MARC algorithms, an enhanced EM-based correction strategy is developed to further boost the retention-error endurance of flash memory while avoiding excessive memory-sensing overhead. Theoretical analyses and simulation results illustrate the superiority of the proposed correction mehtods in terms of the robustness against retention errors.

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Cited By

Hu HHan GWu WLiu C(2024)Channel Parameter and Read Reference Voltages Estimation in 3-D NAND Flash Memory Using Unsupervised Learning AlgorithmsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.330697843:1(305-318)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3306978

Index Terms

Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory
1. Applied computing
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Non-volatile memory

Index terms have been assigned to the content through auto-classification.

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Published: 01 October 2022

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Cited By

Hu HHan GWu WLiu C(2024)Channel Parameter and Read Reference Voltages Estimation in 3-D NAND Flash Memory Using Unsupervised Learning AlgorithmsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.330697843:1(305-318)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3306978

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