An Ising Model-Based Parallel Tempering Processing Architecture for Combinatorial Optimization
Authors: 
Yang Zhang, Xiangrui Wang, Gaopeng Fan, Yuan Cao, Yiqiu Liu, Yongkui Yang, Enyi YaoAuthors Info & Claims
Yang Zhang, Xiangrui Wang, Gaopeng Fan, Yuan Cao, Yiqiu Liu, Yongkui Yang, Enyi YaoAuthors Info & ClaimsPages 4572 - 4584
Abstract
Combinatorial optimization problems (COPs) are prevalent in various domains and present formidable challenges for modern computers. Searching for the ground state of the Ising model emerges as a promising approach to solve these problems. Recent studies have proposed some annealing processing architectures based on the Ising model, aimed at accelerating the solution of COPs. However, most of them suffer from low solution accuracy and inefficient parallel processing. This article presents a novel parallel tempering processing architecture (PTPA) based on the fully connected Ising model to address these issues. The proposed modified parallel tempering algorithm supports multispin concurrent updates per replica and employs an efficient multireplica swap scheme, with fast speed and high accuracy. Furthermore, an independent pipelined spin update architecture is designed for each replica, which supports replica scalability while enabling efficient parallel processing. The PTPA prototype is implemented on FPGA with eight replicas, each with 1024 fully connected spins. It supports up to 64 spins for concurrent updates per replica and operates at 200 MHz. Different concurrency strategies are considered to further improve the efficiency of solving COPs. In the test of various G-set problems, PTPA achieves <inline-formula> <tex-math notation="LaTeX">$3.2\times $ </tex-math></inline-formula> faster solution speed along with 0.27% better average cut accuracy compared to a state-of-the-art FPGA-based Ising machine.
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