IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

In this article, an overall optimization strategy of power amplifier (PA) based on Bayesian algorithm is proposed to perform multiple multiobjective optimization design of sequential load modulated balanced amplifier (SLMBA). Specifically, by combining ...

The novelty of this article is proposing an optimization strategy to design a high-efficiency load modulated balanced amplifier (LMBA) for integrated sensing and communication applications. Taking account of the operating characteristics, theoretical ...

The design of active array structures in analog circuits requires careful matching to minimize the impact of variations. This work presents a constructive approach for building these arrays to directly incorporate shifts due to process variations, ...

Since the data rates in advanced chips dramatically increase, the electrostatic-discharge (ESD) protection circuit at I/O ports causes significant ultrawideband challenges. To address these challenges, an arbitrarily tapped coil (AT-coil) structure with ...

Despite the effort of analog circuit design automation, currently complex analog circuit design still requires extensive manual iterations, making it labor intensive and time-consuming. Recently, reinforcement learning (RL) algorithms have been ...

Exploiting the error tolerance in computation, approximate circuits become an emerging computing paradigm to increase the energy efficiency in digital systems, which is crucial in high-performance and low-power systems for the Edge Internet of Things (...

Modern system-on-chip (SoC) functionalities include significant software interacting closely with low-level hardware to realize system functionalities. This software is developed concurrently with the hardware and must be validated before the hardware is ...

Static or leakage power, which is especially prominent in advanced technology nodes, enables so-called static power side-channel attacks (S-PSCAs). While countermeasures exist, they often incur considerable overheads. Besides, hardware Trojans represent ...

It is well-studied that quantum computing breaks the security of the current worldwide implemented public key cryptosystems. This forces us toward post quantum cryptography (PQC) whose security remains solid even against adversaries having access to ...

Modern advanced CPU designs are frequently exposed to transient execution vulnerabilities, which allow attackers to harness microarchitectural side effects for data exfiltration. The leaked data may encompass direct target data, such as RSA keys or ...

With the drive toward ever more intelligent devices, neural networks (NNs) are deployed on smaller and smaller systems. For these embedded microcontrollers, memory consumption becomes a significant challenge. We propose multiple encoding schemes that ...

Since cloud service providers adopt the sharing mode to improve the utilization of solid state drives (SSDs) and reduce management costs, fairness is a critical design consideration and has drawn great interest in recent years. There are many methods to ...

With the increasing deployment in mission-critical domains, it is of foremost importance to improve dependability of distributed real-time applications for cyber–physical systems (CPSs) with safety & security-critical threats. Different from ...

Directed acyclic graph (DAG) tasks are widely used to model parallel real-time workload. The real-time performance of a DAG task not only depends on its total workload but also its graph structure. Intuitively, with the same total workload, a DAG task ...

The prohibitive complexity of convolutional neural networks (CNNs) has triggered an increasing demand for network simplification. To this end, one natural solution is to remove the redundant channels or layers to explore simplified network structures. ...

Energy harvesting is considered to be a substitute for batteries in many modern systems. Systems based on energy harvesting receive environmental energies from sources, such as sun, radio frequency, wind, vibration, etc, and convert them to electrical ...

Resistive random access memory (ReRAM)-based processing-in-memory (PIM) architectures have demonstrated great potential to accelerate the deep neural network (DNN) training/inference. However, the computational accuracy of analog PIM is compromised due to ...

Combinatorial optimization problems (COPs) are prevalent in various domains and present formidable challenges for modern computers. Searching for the ground state of the Ising model emerges as a promising approach to solve these problems. Recent studies ...

A digital processing-in-memory (PIM) that integrates computing units (CUs) with DRAM banks emerges as a promising technique for accelerating matrix–vector multiplication (MV). However, activating and precharging all banks incur significant ...

2.5-D integration offers a cost-effective and reliable solution for implementing large-scale modular systems. A 2.5-D chiplet system can be designed by connecting smaller chiplets through an interposer, where the chiplets may have heterogeneous ...

Computing-in-memory (CIM) architectures based on various devices, such as resistive random access memory, SRAM, DRAM, etc., have demonstrated promising energy efficiency. Single-device-based CIM chips show different advantages on performance, power, or ...

This article presents an area-efficient Barrett modular multiplication (BMM) algorithm, facilitating the development of cryptosystems like fully homomorphic encryption. Instead of implementing three normal multiplications required by classic BMM, our ...

Although spatial programmable architectures have demonstrated high-performance and programmability for a variety of applications, they suffer from the pipeline unbalancing issue which restricts resource utilization and degrades the performance. In this ...

Recently, there has been increased emphasis on privacy-preserving computation technologies, such as homomorphic encryption (HE) and zero-knowledge proof (ZKP). Modular multiplication is a critical component for both HE and ZKP. Variable bit-width is a ...

Modern logic synthesis techniques use multilevel technology-independent representations like and-inverter-graphs (AIGs) for digital logic. This involves structural rewriting, resubstitution, and refactoring based on directed-acyclic-graph (DAGs) ...

Identification of a threshold function (TF) is a significant task that determines whether a given Boolean function is a TF or not. The state-of-the-art only identifies all 8-input NP-class TFs. In this article, we propose a new necessary condition for a ...

Manual register transfer level (RTL) design and optimization remains prevalent across the semiconductor industry because commercial logic and high-level synthesis tools are unable to match human designs. Our experience in industrial datapath design ...

As DNNs are developing rapidly, the computational and memory burden imposed on hardware systems grows exponentially. This becomes even more severe for large language models (LLMs) and multimodal models. As a promising solution that achieves high ...

We propose switching activity factor-based effective current source model (SAFE) for aging-aware static timing analysis (STA), a new technique for estimating the timing performance of digital circuits. SAFE is based on the development of device-level ...

The input vector-oriented reliability estimation of sequential circuits plays an important role in predicting their reliability boundaries and identifying their reliability-critical gates. This article presents an input vector-oriented programmable method ...