article

Flip-flop energy/performance versus clock slope and impact on the clock network design

Authors:

Massimo Alioto,

Gaetano PalumboAuthors Info & Claims

IEEE Transactions on Circuits and Systems Part I: Regular Papers, Volume 57, Issue 6

Pages 1273 - 1286

https://doi.org/10.1109/TCSI.2009.2030113

Published: 01 June 2010 Publication History

Abstract

In this paper, the influence of the clock slope on the speed of various classes of flip-flops (FFs) and on the overall energy dissipation of both FFs and clock domain buffers is analyzed. Analysis shows that an optimum clock slope exists, which minimizes the energy spent in a clock domain. Results show that the clock slope requirement can be relaxed with respect to traditional assumptions, leading up to 30 ÷ 40 % energy savings and at a very small speed performance penalty. The effectiveness of the clock slope optimization is discussed in detail for the existing classes of FFs. The impact of such an optimization in terms of additive skew and jitter contributions is discussed, together to the analysis of the impact of technology scaling. Extensive post-layout simulations on a 65-nm CMOS technology are performed to check the validity of the underlying assumptions and approximations.

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Cited By

Karimi ARezai AHajhashemkhani M(2018)A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage powerIntegration, the VLSI Journal10.1016/j.vlsi.2017.09.00260:C(160-166)Online publication date: 1-Jan-2018
https://dl.acm.org/doi/10.1016/j.vlsi.2017.09.002
Pouiklis GSirakoulis G(2016)Clock gating methodologies and toolsInternational Journal of Circuit Theory and Applications10.1002/cta.210744:4(798-816)Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1002/cta.2107
Crupi FAlioto MFranco JMagnone PKaczer BGroeseneken GMitard JWitters LHoffmann T(2012)Buried silicon-Germanium pMOSFETsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.215987020:8(1487-1495)Online publication date: 1-Aug-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2159870
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cover image IEEE Transactions on Circuits and Systems Part I: Regular Papers

IEEE Transactions on Circuits and Systems Part I: Regular Papers Volume 57, Issue 6

June 2010

292 pages

ISSN:1549-8328

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IEEE Press

Publication History

Published: 01 June 2010

Accepted: 20 July 2009

Revised: 19 May 2009

Received: 15 January 2009

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Cited By

Karimi ARezai AHajhashemkhani M(2018)A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage powerIntegration, the VLSI Journal10.1016/j.vlsi.2017.09.00260:C(160-166)Online publication date: 1-Jan-2018
https://dl.acm.org/doi/10.1016/j.vlsi.2017.09.002
Pouiklis GSirakoulis G(2016)Clock gating methodologies and toolsInternational Journal of Circuit Theory and Applications10.1002/cta.210744:4(798-816)Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1002/cta.2107
Crupi FAlioto MFranco JMagnone PKaczer BGroeseneken GMitard JWitters LHoffmann T(2012)Buried silicon-Germanium pMOSFETsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.215987020:8(1487-1495)Online publication date: 1-Aug-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2159870
Ribas RSun YReis AIvanov ACavalcanti AMelcher EBecker J(2011)Ring oscillators for functional and delay test of latches and flip-flopsProceedings of the 24th symposium on Integrated circuits and systems design10.1145/2020876.2020893(67-72)Online publication date: 30-Aug-2011
https://dl.acm.org/doi/10.1145/2020876.2020893
Lanuzza MDe Rose RFrustaci FPerri SCorsonello P(2010)Impact of process variations on pulsed flip-flopsProceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation10.5555/1950238.1950261(180-189)Online publication date: 7-Sep-2010
https://dl.acm.org/doi/10.5555/1950238.1950261
Alioto MConsoli EPalumbo G(2010)Physical design aware comparison of flip-flops for high-speed energy-efficient VLSI circuitsProceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation10.5555/1950238.1950247(62-72)Online publication date: 7-Sep-2010
https://dl.acm.org/doi/10.5555/1950238.1950247

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