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Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA

Published: 01 January 2012 Publication History

Abstract

The design of adders on quantum dot cellular automata (QCA) has been of recent interest. While few designs exist, investigations on reduction of QCA primitives (majority gates and inverters) for various adders are limited. In this paper, we present a number of new results on majority logic. We use these results to present efficient QCA designs for the ripple carry adder (RCA) and various prefix adders. We derive bounds on the number of majority gates for $n$-bit RCA and $n$-bit Brent–Kung, Kogge–Stone, Ladner–Fischer, and Han–Carlson adders. We further show that the Brent–Kung adder has lower delay than the best existing adder designs as well as other prefix adders. In addition, signal integrity and robustness studies show that the proposed Brent–Kung adder is fairly well-suited to changes in time-related parameters as well as temperature. Detailed simulations using QCADesigner are presented.

Cited By

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  • (2024)Design and implementation of carry-save adder using quantum-dot cellular automataThe Journal of Supercomputing10.1007/s11227-023-05532-580:2(1554-1567)Online publication date: 1-Jan-2024
  • (2024)Design of an Area Efficient and High-Performance Adder with a Novel Sum GeneratorCircuits, Systems, and Signal Processing10.1007/s00034-024-02724-z43:9(5897-5911)Online publication date: 1-Sep-2024
  • (2023)A Survey of Majority Logic Designs in Emerging Nanotechnologies for ComputingIEEE Transactions on Nanotechnology10.1109/TNANO.2023.332619922(732-739)Online publication date: 1-Jan-2023
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cover image IEEE Transactions on Nanotechnology
IEEE Transactions on Nanotechnology  Volume 11, Issue 1
January 2012
210 pages

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IEEE Press

Publication History

Published: 01 January 2012

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Cited By

View all
  • (2024)Design and implementation of carry-save adder using quantum-dot cellular automataThe Journal of Supercomputing10.1007/s11227-023-05532-580:2(1554-1567)Online publication date: 1-Jan-2024
  • (2024)Design of an Area Efficient and High-Performance Adder with a Novel Sum GeneratorCircuits, Systems, and Signal Processing10.1007/s00034-024-02724-z43:9(5897-5911)Online publication date: 1-Sep-2024
  • (2023)A Survey of Majority Logic Designs in Emerging Nanotechnologies for ComputingIEEE Transactions on Nanotechnology10.1109/TNANO.2023.332619922(732-739)Online publication date: 1-Jan-2023
  • (2022)An Area-Efficient Majority Logic-Based Approximate Adders with Low Delay for Error-Resilient ApplicationsCircuits, Systems, and Signal Processing10.1007/s00034-022-02014-641:9(4977-4997)Online publication date: 1-Sep-2022
  • (2021)A new sign detection design for the residue number system based on quantum-dot cellular automataPhotonic Network Communications10.1007/s11107-021-00941-z42:1(70-80)Online publication date: 1-Aug-2021
  • (2021)The design, analysis, and cost estimation of a generic adder and subtractor using the layered T (LT) logic reduction methodology with a quantum-dot cellular-automata-based approachJournal of Computational Electronics10.1007/s10825-021-01712-920:4(1611-1624)Online publication date: 1-Aug-2021
  • (2020)Design and Implementation of Approximate DCT Architecture in Quantum-Dot Cellular AutomataIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.301372428:12(2530-2539)Online publication date: 1-Dec-2020
  • (2019)Design and analysis of efficient QCA reversible addersThe Journal of Supercomputing10.1007/s11227-018-2683-075:4(2106-2125)Online publication date: 1-Apr-2019
  • (2019)Efficient design of QCA based hybrid multiplier using clock zone based crossoverAnalog Integrated Circuits and Signal Processing10.1007/s10470-019-01570-3102:1(63-77)Online publication date: 16-Dec-2019
  • (2019)A systematic approach towards fault-tolerant design of QCA circuitsAnalog Integrated Circuits and Signal Processing10.1007/s10470-018-1270-x98:3(501-515)Online publication date: 1-Mar-2019
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