article

Design and analysis of efficient QCA reversible adders

Authors:

Mostafa Rahimi Azghadi,

Keivan NaviAuthors Info & Claims

The Journal of Supercomputing, Volume 75, Issue 4

Pages 2106 - 2125

https://doi.org/10.1007/s11227-018-2683-0

Published: 01 April 2019 Publication History

Abstract

Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS technology. In a QCA structure, information destruction plays an essential role in the overall heat dissipation, and in turn in the power consumption of the system. Therefore, reversible logic, which significantly controls the information flow of the system, is deemed suitable to achieve ultra-low-power structures. In order to benefit from the opportunities QCA and reversible logic provide, in this paper, we first review and implement prior reversible full-adder art in QCA. We then propose a novel reversible design based on three- and five-input majority gates, and a robust one-layer crossover scheme. The new full-adder significantly advances previous designs in terms of the optimization metrics, namely cell count, area, and delay. The proposed efficient full-adder is then used to design reversible ripple-carry adders (RCAs) with different sizes (i.e., 4, 8, and 16 bits). It is demonstrated that the new RCAs lead to 33% less garbage outputs, which can be essential in terms of lowering power consumption. This along with the achieved improvements in area, complexity, and delay introduces an ultra-efficient reversible QCA adder that can be beneficial in developing future computer arithmetic circuits and architectures.

References

[1]

Bennett CH (1973) Logical reversibility of computation. IBM J Res Dev 17:525---532

Digital Library

[2]

Landauer R (1961) Irreversibility and heat generation in the computational process. IBM J Res Dev 5:183---191

Digital Library

[3]

Heikalabad SR, Asfestani MN, Hosseinzadeh M (2018) A full adder structure without cross-wiring in quantum-dot cellular automata with energy dissipation analysis. J Supercomput 74:1994---2005

Digital Library

[4]

Hänninen I, Takala J (2010) Binary adders on quantum-dot cellular automata. J Signal Process Syst 58:87---103.

Digital Library

[5]

Tougaw PD, Lent CS (1994) Logical devices implemented using quantum cellular automata. J Appl Phys Am Inst Phys 75:1818---1824

[6]

Wang W, Walus K, Jullien GA (2003) Quantum-dot cellular automata adders. In: Proceedings of IEEE Conference on Nanotechnology, pp 461---464

[7]

Pudi V, Sridharan K (2012) Low complexity design of ripple carry and Brent-Kung adders in QCA. IEEE Trans Nanotechnol 11:105---119

Digital Library

[8]

Rahimi Azghadi M, Kavehei O, Navi K (2007) A novel design for quantum-dot cellular automata cells and full-adders. J Appl Sci 7:3460---3468

[9]

Hashemi S, Navi K (2015) A novel robust QCA full-adder. Procedia Mater Sci 11:376---380

[10]

Mohammadi M, Mohammadi M, Gorgin S (2016) An efficient design of full adder in quantum-dot cellular automata (QCA) technology. Microelectron J 50:35---43

Digital Library

[11]

Sayedsalehi S, Azghadi MR, Angizi S, Navi K (2015) Restoring and non-restoring array divider designs in quantum-dot cellular automata. Inf Sci 31:86---101

Digital Library

[12]

Ahmadpour SS, Mosleh MJ (2018) A novel fault-tolerant multiplexer in quantum-dot cellular automata technology. J Supercomput.

Digital Library

[13]

Hashemi S, Navi K (2012) New robust QCA D flip flop and memory structures. Microelectron J 43(12):929---940

Digital Library

[14]

Vetteth A, Walus K, Dimitrov VS, Jullien GA (2003) Quantum-dot cellular automata of flip-flops. ATIPS Laboratory 2500 University Drive, N.W., Calgary, Alberta, Canada T2 N1N4

[15]

Yang X, Cai L, Zhao X (2010) Low power dual-edge triggered flip-flop structure in quantum dot cellular automata. Electron Lett 46:825---826

[16]

Murphy SF, Ottavi M, Frank M, DeBenedictis E (2006) On the design of reversible QDCA systems. Sandia National Laboratories, Albuquerque, NM, Tech. Rep. SAND2006-5990

[17]

Thapliyal H, Ranganathan N (2010) Reversible logic-based concurrently testable latches for molecular QCA. IEEE Trans Nanotechnol 9(1):62---69

Digital Library

[18]

Thapliyal H, Ranganathan N, Kotiyal S (2013) Design of testable reversible sequential circuits. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(7):1201---1209

Digital Library

[19]

Shah NA, Khanday FA, Iqbal J (2012) Quantum-dot cellular automata (QCA) design of multi-function reversible logic gate. Commun Inf Sci Manag Eng (CISME) 2(4):8---18

[20]

Hashemi S, Navi K (2014) Reversible multiplexer design in quantum-dot cellular automata. Quantum Matter (ASP) 6:523---528

[21]

Kianpour M, Sabbaghi-Nadooshan R (2017) Novel 8-bit reversible full-adder/subtractor using a QCA reversible gate. J Comput Electron 16:459---472

Digital Library

[22]

Taherkhani E, Moaiyeri MH, Angizi S (2017) Design of an ultra-efficient reversible full adder-subtractor in quantum-dot cellular automata. Optik Int J Light Electron Opt 142:557---563

[23]

Al-Shafi MA, Islam MS, Newaz Bahar A (2015) A review on reversible logic gates and it's QCA implementation. IJCA 128(2). http://www.ijcaonline.org/archives/volume128/number2/22845-2015906434

[24]

Ma X, Huang J, Metra C, Lombardi F (2008) Reversible gates and testability of one dimensional arrays of molecular QCA. J Electron Test 24(1):297---311

Digital Library

[25]

Hashemi S, Navi K (2014) Designing quantum-dot cellular automata circuits using a robust one layer crossover scheme. IET J Eng.

[26]

Kim K, Wu K, Karri R (2007) The robust QCA adder designs using composable QCA building blocks. IEEE Trans Comput Aided Des Integr Circuits Syst 26:176---183

Digital Library

[27]

Kim K, Wu K, Karri R (2005) Towards designing robust QCA architectures in the presence of sneak noise paths. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp 1214---1219

Digital Library

[28]

Devadoss R, Paul K, Balakrishnan M (2009) Coplanar QCA crossovers. IET Electron Lett 45:1234---1235

[29]

Tougaw D, Khatun M (2013) A scalable signal distribution network for quantum-dot cellular automata. IEEE Trans Nanotechnol 12:215---224

Digital Library

[30]

Shin SH, Jeon JC, Yoo KY (2013) Wire-crossing technique on quantum-dot cellular automata. In: Second International Conference Next Generation Computer and Information Technology (NGCIT), pp 52---57

[31]

Toffoli T (1980) Reversible computing. In: Proceedings of the 7th Colloquium on Automata, Languages and Programming. Springer, London, UK, pp 632---644

Digital Library

[32]

Peres A (1985) Reversible logic and quantum computers. Phys Rev A Gen Phys 32(6):3266---3276

[33]

Fredkin E, Toffoli T (1982) Conservative logic. Int J Theor Phys 21:219---253

[34]

Smolin JA, Divincenzo DP (1996) Five two-bit quantum gates are sufficient to implement the quantum Fredkin gate. Phys Rev A 53:2855---2856

[35]

Thapliyal H, Arabnia HR, Srinivas MB (2009) Efficient reversible logic design of BCD subtractors. In: Transactions on Computational Science Journal, Vol. III. Springer, LNCS 5300, pp 99---121

Digital Library

[36]

Thapliyal H, Arabnia HR, Bajpai R, Sharma KK (2007) Combined integer and variable precision (CIVP) floating point multiplication architecture for FPGAs. In: Proceedings of 2007 International Conference on Parallel and Distributed Processing Techniques and Applications; PDPTA'07, Vol 2207, USA, pp 449---450

[37]

Thapliyal H, Arabnia HR (2006) Reversible programmable logic array (RPLA) using Fredkin and Feynman gates for industrial electronics and applications. In: Proceedings of 2006 International Conference on Computer Design and Conference on Computing in Nanotechnology (CDES'06: June 26-29, 2016; Las Vegas, USA), pp 70---74

[38]

Thapliyal H, Srinivas MB, Arabnia HR (2005) Reversible logic synthesis of half, full and parallel subtractors. In: Proceedings of 2005 international conference on embedded systems and applications, ESA'05, June, Las Vegas, pp 165---172

[39]

Thapliyal H, Jayashree HV, Nagamani AN, Arabnia HR (2013) Progress in reversible processor design: a novel methodology for reversible carry look-ahead adder. In: Gavrilova ML, Tan CJK (eds) Transactions in computational science (Springer), XVII, LNCS 7420. Springer, Berlin, pp 73---97

[40]

Thapliyal H, Ranganathan N (2010) Design of reversible sequential circuits optimizing quantum cost. Delay Garbage Outputs JETC 6(4):14---31

Digital Library

[41]

Azad Khan MMH (2002) Design of full-adder with reversible gates. In: International Conference on Computer and Information Technology, Dhaka, pp 515---519

[42]

Khlopotine AB, Perkowski M, Kerntopf P (2002) Reversible logic synthesis by iterative composition. In: Proceedings of IWLS, 2002, pp 261---266

[43]

Bruce JW, Thornton MA, Shivakumaraiah L, Kokate PS, Li X (2002) Efficient adder circuits based on a conservative reversible logic gate. In: IEEE Computer Society Annual Symposium on VLSI, pp 74---79

Digital Library

[44]

Babu HH, Islam R, Chowdhury AR, Chowdhury SMA (2003) On the realization of reversible full-adder circuit. In: International Conference on Computer and Information Technology, Dhaka, Bangladesh, pp 880---883

[45]

Babu HMH, Islam MR, Chowdhury AR, Chowdhury SMA (2003) Reversible logic synthesis for minimization of full adder circuit. In Proceedings of the Euro Micro Symposium on Digital System Design (DSD"03), Belek-Antalya, Turkey, pp 50---54

Digital Library

[46]

Thapliyal H, Srinivas MB (2005) A novel reversible TSG gate and its application for designing reversible carry look-ahead and other adder architectures. In: Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture (ACSAC"05), pp 805---817

Digital Library

[47]

Thapliyal H, Srinivas MB (2005) Novel design and reversible logic synthesis of multiplexer based full adder and multipliers. In: 48th Midwest Symposium on Circuits and Systems, vol 2, pp 1593---1596

[48]

Islam S, Islam R (2005) Minimization of reversible adder circuits. Asian J Inf Technol 4(12):1146---1151

[49]

Babu HMH, Chowdhury AR (2006) Design of a compact reversible binary coded decimal adder circuit. J Syst Archit 52:272---282

Digital Library

[50]

Thapliyal H, Vinod AP (2007) Designing efficient online testable reversible adders with new reversible gate. In: Proceedings of ISCAS 2007, New Orleans, USA, pp 1085---1088

[51]

Haghparasat M, Navi K (2008) A novel reversible full adder circuit for nanotechnology based systems. J Appl Sci 7:3995---4000

[52]

Haghparast M, Navi K (2008) A novel reversible BCD adder for nanotechnology based systems. Am J Appl Sci 5(3):282---288

[53]

Saiful Islam M (2009) A novel quantum cost efficient reversible full adder gate in nanotechnology. http://arxiv.org/abs/1008.3533

[54]

Ni L, Guan Z, Zhu W (2010) A general method of constructing the reversible full-adder. In: Third International Symposium on Intelligent Information Technology and Security Informatics (IITSI), pp 109---113

Digital Library

[55]

Sengupta D, Sultana M, Chaudhuri A (2011) Realization of a novel reversible SCG gate and its application for designing parallel adder/subtractor and match logic. Int J Comput Appl 31:30---35

[56]

AnanthaLakshmi AV, Sudha GF (2013) Design of a novel reversible full adder and reversible full subtractor. Adv Intell Syst Comput 178:623---632

[57]

Kunalan D, Cheong CL, Chau CF, Ghazali AB (2014) Design of a 4-bit adder using reversible logic in quantum-dot cellular automata (QCA). In: Proceedings of IEEE-ICSE2014, Kuala Lumpur

[58]

Mohammadi Z, Mohammadi M (2014) Implementing a one-bit reversible full adder using quantum-dot cellular automata. Quantum Inf Process 13:2127---2147

Digital Library

Cited By

Navimipour NAhmadpour SYalcin S(2024)A nano-scale arithmetic and logic unit using a reversible logic and quantum-dotsThe Journal of Supercomputing10.1007/s11227-023-05491-x80:1(395-412)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1007/s11227-023-05491-x
Dhar MMukherjee CBanerjee AManna DPanda SMaji B(2024)Predicting Energy Dissipation in QCA-Based Layered-T Gates Under Cell Defects and Polarisation: A Study with Machine-Learning ModelsJournal of Electronic Testing: Theory and Applications10.1007/s10836-024-06133-740:4(435-455)Online publication date: 21-Aug-2024
https://dl.acm.org/doi/10.1007/s10836-024-06133-7
Jain VSharma DGaur HSingh AWen X(2023)Comprehensive and Comparative Analysis of QCA-based Circuit Designs for Next-generation ComputationACM Computing Surveys10.1145/362293256:5(1-36)Online publication date: 25-Nov-2023
https://dl.acm.org/doi/10.1145/3622932
Show More Cited By

Design and analysis of efficient QCA reversible adders
1. Hardware

Recommendations

Realizing Reversible Computing in QCA Framework Resulting in Efficient Design of Testable ALU
Special Issue on Computational Synthetic Biology and Regular Papers

Reversible logic is emerging as a prospective logic design style for implementing ultra-low-power VLSI circuits. It promises low-power consuming circuits by nullifying the energy dissipation in irreversible logic. On the other hand, as a potential ...
Optimized reversible binary-coded decimal adders

Babu and Chowdhury [H.M.H. Babu, A.R. Chowdhury, Design of a compact reversible binary coded decimal adder circuit, Journal of Systems Architecture 52 (5) (2006) 272-282] recently proposed, in this journal, a reversible adder for binary-coded decimals. ...
Novel 8-bit reversible full adder/subtractor using a QCA reversible gate

Conventional digital circuits consume a considerable amount of energy. If bits of information remain during logical operations, power consumption decreases considerably because the data bits in reversible computations are not lost. The types of ...

Comments

Information & Contributors

Information

Published In

cover image The Journal of Supercomputing

The Journal of Supercomputing Volume 75, Issue 4

April 2019

542 pages

ISSN:0920-8542

Issue’s Table of Contents

Copyright © Copyright © 2019 Springer Science+Business Media, LLC, part of Springer Nature.

Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 April 2019

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

9
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 13 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Navimipour NAhmadpour SYalcin S(2024)A nano-scale arithmetic and logic unit using a reversible logic and quantum-dotsThe Journal of Supercomputing10.1007/s11227-023-05491-x80:1(395-412)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1007/s11227-023-05491-x
Dhar MMukherjee CBanerjee AManna DPanda SMaji B(2024)Predicting Energy Dissipation in QCA-Based Layered-T Gates Under Cell Defects and Polarisation: A Study with Machine-Learning ModelsJournal of Electronic Testing: Theory and Applications10.1007/s10836-024-06133-740:4(435-455)Online publication date: 21-Aug-2024
https://dl.acm.org/doi/10.1007/s10836-024-06133-7
Jain VSharma DGaur HSingh AWen X(2023)Comprehensive and Comparative Analysis of QCA-based Circuit Designs for Next-generation ComputationACM Computing Surveys10.1145/362293256:5(1-36)Online publication date: 25-Nov-2023
https://dl.acm.org/doi/10.1145/3622932
Rajasekar PMangalam HKumar C(2022)Logic Realization of Galois Field for AES SBOX using Quantum Dot Cellular AutomataThe Journal of Supercomputing10.1007/s11227-022-04779-879:3(3024-3054)Online publication date: 29-Aug-2022
https://dl.acm.org/doi/10.1007/s11227-022-04779-8
Ahmadpour SMosleh MRasouli Heikalabad S(2022)Efficient designs of quantum-dot cellular automata multiplexer and RAM with physical proof along with power analysisThe Journal of Supercomputing10.1007/s11227-021-03913-278:2(1672-1695)Online publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1007/s11227-021-03913-2
Roy RSarkar SDhar S(2021)Design and testing of a reversible ALU by quantum cells automata electro-spin technologyThe Journal of Supercomputing10.1007/s11227-021-03767-877:12(13601-13628)Online publication date: 1-Dec-2021
https://dl.acm.org/doi/10.1007/s11227-021-03767-8
Foroutan SSabbaghi-Nadooshan RMohammadi MTavakoli M(2021)Investigating multiple defects on a new fault-tolerant three-input QCA majority gateThe Journal of Supercomputing10.1007/s11227-020-03567-677:8(8305-8325)Online publication date: 1-Aug-2021
https://dl.acm.org/doi/10.1007/s11227-020-03567-6
Ahmadpour SMosleh MRasouli Heikalabad S(2020)The design and implementation of a robust single-layer QCA ALU using a novel fault-tolerant three-input majority gateThe Journal of Supercomputing10.1007/s11227-020-03249-376:12(10155-10185)Online publication date: 1-Dec-2020
https://dl.acm.org/doi/10.1007/s11227-020-03249-3
Das JDe D(2019)Novel design of reversible priority encoder in quantum dot cellular automata based on Toffoli gate and Feynman gateThe Journal of Supercomputing10.1007/s11227-019-02904-875:10(6882-6903)Online publication date: 1-Oct-2019
https://dl.acm.org/doi/10.1007/s11227-019-02904-8

View Options

View options

Media

Figures

Other

Tables

View Issue’s Table of Contents