research-article

Designing via-configurable logic blocks for regular fabric

Authors:

Malgorzata Marek-SadowskaAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 14, Issue 1

Pages 1 - 14

https://doi.org/10.1109/TVLSI.2005.863196

Published: 01 January 2006 Publication History

Abstract

In this paper, we describe the design process of a viaconfigurable logic block for regular fabric. The block consists of a via-configurable functional cell and two via-configurable inverter arrays. A via-configurable functional cell can efficiently implement most commonly used CMOS static cells, and a via-configurable inverter array is efficient in implementing inverters, repeaters, and some pass-transistor logic. The cells have prefabricated transistors, contacts, and M1 wires. The M2 mask is fixed. All of the functions can be realized by customizing only an M1-M2 via mask. We construct a general-purpose fabric based on the via-configurable block and show its great flexibility in implementing a variety of functions. Compared to other fabrics based on look-up tables or programmable logic arrays, our fabric has much higher performance, smaller area, and lower power consumption.

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Cited By

Bobba SDe Micheli G(2015)Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles ArchitectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.235888423:10(2103-2115)Online publication date: 23-Sep-2015
https://dl.acm.org/doi/10.1109/TVLSI.2014.2358884
Lin TLin KChiu CLin RCavallaro JZhang TJones ALi H(2014)Logic block and design methodology for via-configurable structured ASIC using dual supply voltagesProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591601(111-116)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2591513.2591601
Gaillardon PAmarù LBobba SDe Marchi MSacchetto DLeblebici YDe Micheli GMacii E(2013)Vertically-stacked double-gate nanowire FETs with controllable polarityProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485442(625-630)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485442
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Designing via-configurable logic blocks for regular fabric
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 14, Issue 1

January 2006

94 pages

ISSN:1063-8210

Issue’s Table of Contents

Copyright © 2006.

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 January 2006

Revised: 14 July 2005

Received: 09 March 2005

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Cited By

Bobba SDe Micheli G(2015)Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles ArchitectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.235888423:10(2103-2115)Online publication date: 23-Sep-2015
https://dl.acm.org/doi/10.1109/TVLSI.2014.2358884
Lin TLin KChiu CLin RCavallaro JZhang TJones ALi H(2014)Logic block and design methodology for via-configurable structured ASIC using dual supply voltagesProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591601(111-116)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2591513.2591601
Gaillardon PAmarù LBobba SDe Marchi MSacchetto DLeblebici YDe Micheli GMacii E(2013)Vertically-stacked double-gate nanowire FETs with controllable polarityProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485442(625-630)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485442
Tsai MHsu PLi HHung YLiu Y(2013)Routability optimization for crossbar-switch structured ASIC designACM Transactions on Design Automation of Electronic Systems10.1145/2491477.249148318:3(1-28)Online publication date: 29-Jul-2013
https://dl.acm.org/doi/10.1145/2491477.2491483
Ho MAi YChau TYuen SChoy CLeong PPun K(2013)Architecture and design flow for a highly efficient structured ASICIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.219047821:3(424-433)Online publication date: 1-Mar-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2190478
Tsai HLin RLai LRosenstiel WMacii E(2012)Design and analysis of via-configurable routing fabrics for structured ASICsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493070(1479-1482)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2493070
Pons MMorgan MPiguet CRosenstiel WMacii E(2012)Fixed origin corner square inspection layout regularity metricProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493049(1397-1402)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2493049
Bobba SGaillardon PZhang JDe Marchi MSacchetto DLeblebici YDe Micheli GMoritz C(2012)Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistorsProceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures10.1145/2765491.2765503(55-60)Online publication date: 4-Jul-2012
https://dl.acm.org/doi/10.1145/2765491.2765503
Bobba SDe Marchi MLeblebici YDe Micheli GGroeneveld PSciuto DHassoun S(2012)Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistorsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228369(42-47)Online publication date: 3-Jun-2012
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Tung HLin RLi MHeish T(2012)Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flowIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217071220:12(2184-2197)Online publication date: 1-Dec-2012
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