Article

River PLAs: a regular circuit structure

Authors:

Fan Mo,

Robert K. BraytonAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 201 - 206

https://doi.org/10.1145/513918.513970

Published: 10 June 2002 Publication History

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Abstract

A regular circuit structure called a River PLA and its re-configurable version, Glacier PLA, are presented. River PLAs provide greater regularity than circuits implemented with standard-cells. Conventional optimization stages such as technology mapping, placement and routing are eliminated. These two features make the River PLA a highly predictable structure. Glacier PLAs can be an alternative to FPGAs, but with a simpler and more efficient design methodology.

References

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E. Sentovich, K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton and A. Sangiovanni-Vincentelli, "SIS: A system for sequential circuit synthesis", Tech. Rep., UCB/ERL M92/41, Electronics Research Lab, University of California, Berkeley, May 1992

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R. Rudell and A. Sangiovanni-Vincentelli, "Multiple-valued minimization for PLA optimization", IEEE Transactions on CAD, vol. 6, Sep 1987, 727--750

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F. Mo, A. Tabbara and R.Brayton, "A Force-Directed Macro-Cell Placer", Proceedings of ICCAD, Nov 2000

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http://www.cbl.ncsu.edu/pub/Benchmark_dirs/LGSynth91/

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Cited By

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Mahdoum A(2020)ReferencesCAD of Circuits and Integrated Systems10.1002/9781119751595.refs(267-272)Online publication date: 24-Jul-2020
https://doi.org/10.1002/9781119751595.refs
Cho MChoudhury MPuri RRen HXiang HNam GMo FBrayton R(2016)Structured Digital DesignElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-9(155-182)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-9
Jayakumar NPaul SGarg RGulati KKhatri SJayakumar NPaul SGarg RGulati KKhatri S(2009)Optimum VDD for Minimum EnergyMinimizing and Exploiting Leakage in VLSI Design10.1007/978-1-4419-0950-3_11(129-142)Online publication date: 20-Oct-2009
https://doi.org/10.1007/978-1-4419-0950-3_11
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Index Terms

River PLAs: a regular circuit structure
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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Published In

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 10 June 2002

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DAC02: 39th Design Automation Conference

June 10 - 14, 2002

Louisiana, New Orleans, USA

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Overall Acceptance Rate 1,317 of 3,929 submissions, 34%

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Mahdoum A(2020)ReferencesCAD of Circuits and Integrated Systems10.1002/9781119751595.refs(267-272)Online publication date: 24-Jul-2020
https://doi.org/10.1002/9781119751595.refs
Cho MChoudhury MPuri RRen HXiang HNam GMo FBrayton R(2016)Structured Digital DesignElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-9(155-182)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-9
Jayakumar NPaul SGarg RGulati KKhatri SJayakumar NPaul SGarg RGulati KKhatri S(2009)Optimum VDD for Minimum EnergyMinimizing and Exploiting Leakage in VLSI Design10.1007/978-1-4419-0950-3_11(129-142)Online publication date: 20-Oct-2009
https://doi.org/10.1007/978-1-4419-0950-3_11
Paul SGarg RKhatri SNarayanan VYan ZMacii EBhanja S(2008)Pipelined network of PLA based circuit designProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366162(213-218)Online publication date: 4-May-2008
https://dl.acm.org/doi/10.1145/1366110.1366162
Jayakumar NGarg RGamache BKhatri SSentovich E(2006)A PLA based asynchronous micropipelining approach for subthreshold circuit designProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147021(419-424)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1147021
Garg RSanchez MGulati KJayakumar NGupta AKhatri SQu GIsmail YNarayanan VZhou H(2006)A design flow to optimize circuit delay by using standard cells and PLAsProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127960(217-222)Online publication date: 30-Apr-2006
https://dl.acm.org/doi/10.1145/1127908.1127960
Ran YMarek-Sadowska M(2006)Designing via-configurable logic blocks for regular fabricIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2005.86319614:1(1-14)Online publication date: 1-Jan-2006
https://dl.acm.org/doi/10.1109/TVLSI.2005.863196
Jayakumar NKhatri S(2005)Minimum Energy Near-threshold Network of PLA based DesignProceedings of the 2005 International Conference on Computer Design10.1109/ICCD.2005.75(399-404)Online publication date: 2-Oct-2005
https://dl.acm.org/doi/10.1109/ICCD.2005.75
Liu YWang KHwang T(2004)Crosstalk Minimization in Logic Synthesis for PLAProceedings of the conference on Design, automation and test in Europe - Volume 210.5555/968879.969174Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968879.969174
Ran YMarek-Sadowska MMalik SFix LKahng A(2004)On designing via-configurable cell blocks for regular fabricsProceedings of the 41st annual Design Automation Conference10.1145/996566.996624(198-203)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996624
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Recommendations

Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays

Logic Design of Programmable Logic Arrays

Design of Crosspoint-Irredundant PLAs Using Minimal Number of Control Inputs

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