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Conditional data mapping flip-flops for low-power and high-performance systems

Published: 01 December 2006 Publication History
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  • Abstract

    This paper introduces a new family of low-power and high-performance flip-flops, namely conditional data mapping flip-flops (CDMFFs), which reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant internal transitions. We present two CDMFFs, having differential and single-ended structures, respectively, and compare them to the state-of-tie-art flip-flops. The results indicate that both CDMFFs have the best power-delay product in their groups, respectively. In the aspect of power dissipation, the single-ended and differential CDMFFs consume the least power at data activity less than 50%, and are 31% and 26% less power than the conditional capture flip-flops at 25% data activity, respectively. In the aspect of performance, CDMFFs achieve small data-to-output delays, comparable to those of the transmission-gate pulsed latch and the modified-sense-amplifier flip-flop. In the aspect of timing reliability, CDMFFs have the best internal race immunity among pulse-triggered flip-flops. A post-layout case study is demonstrated with comparison to a transmission-gate flip-flop. The results indicate the single-ended CDMFF has 34% less in data-to-output delay and 28% less in power at 25% data activity, in spite of the 34% increase in size.

    References

    [1]
    M. Nogawa and Y. Ohtomo, "A data-transition look-ahead DFF circuit for statistical reduction in power consumption," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 702-706, May 1998.
    [2]
    M. Hamada et al., "Flip-flop selection technique for power-delay tradeoff," in ISSCC Dig. Tech. Papers, 1999, pp. 270-271.
    [3]
    N. Nedovic and V. G. Oklobdzija, "Hybrid latch flip-flop with improved power efficiency," in Proc. Symp. Integr. Circuits Syst. Des., 2000, pp. 211-215.
    [4]
    B.-S. Kong, S.-S. Kim, and Y.-H. Jun, "Conditional-capture flip-flop for statistical power reduction," IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1263-1271, Aug. 2001.
    [5]
    P. Zhao, T. K. Darwish, and M. A. Bayoumi, "High-performance and low-power conditional discharge flip-flop," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp. 477-484, May 2004.
    [6]
    B. Nikolic et al., "Improved sense-amplifier-based flip-flop: Design and measurements," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876-883, Jun. 2000.
    [7]
    F. Klass, "Semi-dynamic and dynamic flip-flops with embedded logic," in Symp. VLSI Circuits Dig. Tech. Papers, 1998, pp. 108-109.
    [8]
    H. Partovi et al., "Flow-through latch and edge-triggered flip-flop hybrid elements," in ISSCC Dig. Tech. Papers, 1996, pp. 138-139.
    [9]
    J. Tschanz et al., "Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors," in Int. Symp. Low Power Electron. Des. Tech. Dig., 2001, pp. 147-152.
    [10]
    S.D. Naffziger, "The implementation of the itanium 2 microprocessor," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1448-1460, Nov. 2002.
    [11]
    J. D. Warnock et al., "The circuit and physical design of the POWER4 microprocessor," IBM J. Res. Dev., vol. 46, pp. 27-51, Jan. 2002.
    [12]
    G. Gerosa et al., "A 2.2 W 80 MHz superscalar RISC microprocessor," IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1440-1452, Dec. 1994.
    [13]
    V. Stojanovic and V. G. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems," IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536-548, Apr. 1999.
    [14]
    N. Nedovic, W. W. Walker, and V. G. Oklobdzija, "A test circuit for measurement of clocked storage element characteristics," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1294-1304, Aug. 2004.
    [15]
    D. Markovic, B. Nikolic, and R. W. Brodersen, "Analysis and design of low-energy flip-flops," in Int. Symp. Low Power Electron. Des. Tech. Dig., 2001, pp. 52-55.

    Cited By

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    • (2018)Design of sequential elements for low power clocking systemIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203870519:5(914-918)Online publication date: 29-Dec-2018
    • (2018)Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flopsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202911619:1(1-9)Online publication date: 29-Dec-2018
    • (2010)Design and verification methods of Toshiba's wireless LAN baseband SoCProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899831(457-463)Online publication date: 18-Jan-2010

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    1. Conditional data mapping flip-flops for low-power and high-performance systems

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          Published In

          cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
          IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 14, Issue 12
          December 2006
          108 pages

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          IEEE Educational Activities Department

          United States

          Publication History

          Published: 01 December 2006
          Revised: 25 December 2005
          Received: 04 July 2005

          Author Tags

          1. CMOS digital integrated circuits
          2. flip-flops
          3. high-speed integrated circuits
          4. low-power integrated circuits

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          • (2018)Design of sequential elements for low power clocking systemIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203870519:5(914-918)Online publication date: 29-Dec-2018
          • (2018)Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flopsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202911619:1(1-9)Online publication date: 29-Dec-2018
          • (2010)Design and verification methods of Toshiba's wireless LAN baseband SoCProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899831(457-463)Online publication date: 18-Jan-2010

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